Update

lab2CA.srcs/sources_1/new/BasicModules.v

@@ -259,43 +259,32 @@ module comparator_tb();
 endmodule
 
 module decoder (
-    input wire en,
     input wire [1:0] index,
     output reg [3:0] regOut);
     
-    always @(en, index)begin
-        if(en == 0)begin
-            case(index) 
-            2'b00: regOut <= 4'b1110; 
-            2'b01: regOut <= 4'b1101;
-            2'b10: regOut <= 4'b1011;
-            2'b11: regOut <= 4'b0111;
-            default: regOut <= 4'b1111; 
-            endcase 
-        end
-        else begin
-            regOut <= 4'b1111; 
-        end
-    end
+    always @ (index)
+    case(index) 
+        2'b00: regOut <= 4'b1110; 
+        2'b01: regOut <= 4'b1101;
+        2'b10: regOut <= 4'b1011;
+        2'b11: regOut <= 4'b0111;
+        default: regOut <= 4'b1111; 
+    endcase
 endmodule
 
 //testbench
 module decoder_tb();
-    reg enable;
     reg [1:0] indexIn;
     wire [3:0] regOut;
 
     decoder dec0(
-        .en(enable),
         .index(indexIn),
-        .regOut(regOut));
+        .regOut(regOut)
+    );
     
     initial begin
-        enable = 0;
         indexIn = 2'b00;
         #5
-        enable = 1;
-        #5
         indexIn = 2'b01;
         #5
         indexIn = 2'b10;
@@ -885,7 +874,7 @@ module eMPipReg(
 endmodule 
     
 module shift_left(
-    input wire [8:0] A,
+    input wire [7:0] A,
     output wire [8:0] B);
     
     assign B = {A[7:0],1'b0};
@@ -921,20 +910,20 @@ module shift_left_tb();
     end
 endmodule
 
-module shift_right_logical(
-    input wire [8:0] A,
+module shift_right_arithmetic(
+    input wire [8:1] A,
     output wire [8:0] B);
     
-    assign B = {1'b0,A[8:1]};
+    assign B = {A[8],A[8:1]};
 
 endmodule
 
 //testbench
-module shift_right_logical_tb();
+module shift_right_arithmetic_tb();
     reg [8:0] a;
     wire [8:0] b;
 
-    shift_right_logical tb0(
+    shift_right_arithmetic tb0(
         .A(a),
         .B(b));
 
@@ -958,21 +947,21 @@ module shift_right_logical_tb();
     end
 endmodule
 
-module shift_right_arithmetic(
-    input wire [8:0] A,
+module shift_right_logical(
+    input wire [8:1] A,
     output wire [8:0] B);
     
-    assign B = {A[8],A[8:1]};
+    assign B = {1'b0,A[8:1]};
+    
 
 endmodule
 
-
 //testbench
-module shift_right_arithmetic_tb();
+module shift_right_logical_tb();
     reg [8:0] a;
     wire [8:0] b;
 
-    shift_right_arithmetic tb0(
+    shift_right_logical tb0(
         .A(a),
         .B(b));