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Simplified bitwise OR

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WilliamMiceli
2019-03-12 10:48:50 -04:00
parent e01d639fa0
commit f3ea596086
1 changed files with 1 additions and 82 deletions
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83
lab2CA.srcs/sources_1/new/BasicModules.v
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@@ -536,93 +536,12 @@ module not_9bit_tb();
end
endmodule
module or_1bit(
input wire A,
input wire B,
output wire C);
assign C = A | B;
endmodule
//testbench
module or_1bit_tb();
reg a;
reg b;
wire c;
or_1bit or0(
.A(a),
.B(b),
.C(c));
initial begin
a = 0;
b = 0;
#5
a = 0;
b = 1;
#5
a = 1;
b = 0;
#5
a = 1;
b = 1;
#5
$finish;
end
endmodule
module or_9bit(
input wire [8:0] A,
input wire [8:0] B,
output wire [8:0] C);
or_1bit or0(
.A(A[0]),
.B(B[0]),
.C(C[0]));
or_1bit or1(
.A(A[1]),
.B(B[1]),
.C(C[1]));
or_1bit or2(
.A(A[2]),
.B(B[2]),
.C(C[2]));
or_1bit or3(
.A(A[3]),
.B(B[3]),
.C(C[3]));
or_1bit or4(
.A(A[4]),
.B(B[4]),
.C(C[4]));
or_1bit or5(
.A(A[5]),
.B(B[5]),
.C(C[5]));
or_1bit or6(
.A(A[6]),
.B(B[6]),
.C(C[6]));
or_1bit or7(
.A(A[7]),
.B(B[7]),
.C(C[7]));
or_1bit or8(
.A(A[8]),
.B(B[8]),
.C(C[8]));
assign C = A | B;
endmodule