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Added memories to the CPU

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This commit is contained in:
Johannes
2019-03-16 14:37:46 -04:00
parent 3c8147641f
commit fa5caec5dd
3 changed files with 38 additions and 37 deletions
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28
lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl
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@@ -1,6 +1,6 @@
webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/
webtalk_register_client -client project
webtalk_add_data -client project -key date_generated -value "Sat Mar 16 14:13:55 2019" -context "software_version_and_target_device"
webtalk_add_data -client project -key date_generated -value "Sat Mar 16 14:16:46 2019" -context "software_version_and_target_device"
webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device"
webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device"
@@ -14,7 +14,7 @@ webtalk_add_data -client project -key target_package -value "not_applicable" -co
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "18" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "19" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment"
webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment"
@@ -22,21 +22,11 @@ webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user
webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment"
webtalk_register_client -client xsim
webtalk_add_data -client xsim -key File_Counter -value "2" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Simulation_Image_Code -value "69 KB" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Image_Data -value "3 KB" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Processes -value "24" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Instances -value "3" -context "xsim\\usage"
webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip unimacro_ver unisims_ver " -context "xsim\\usage"
webtalk_add_data -client xsim -key Compiler_Time -value "0.73_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Compiler_Memory -value "38176_KB" -context "xsim\\usage"
webtalk_transmit -clientid 198226099 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage"
webtalk_add_data -client xsim -key runtime -value "60 ns" -context "xsim\\usage"
webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Time -value "0.06_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Memory -value "6112_KB" -context "xsim\\usage"
webtalk_transmit -clientid 2514989005 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_terminate

17
lab2CA.srcs/sources_1/new/CPU9bits.v
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@@ -1,16 +1,29 @@
`timescale 1ns / 1ps
module CPU9bits(
input wire [8:0] instr,
input wire reset, clk,
output wire done
);
wire [8:0] op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut, linkData, SE1N, SE2N, SE3N;
wire [8:0] instr, op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut, linkData, SE1N, SE2N, SE3N;
wire [2:0] FU;
wire [3:0] aluOp;
wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1, link;
instructionMemory iM(
.clk(clk),
.address(PCout),
.readData(instr)
);
dataMemory dM(
.clk(clk),
.writeEnable(loadS),
.writeData(op0),
.address(AluOut),
.readData(dataMemOut)
);
RegFile RF(
.clk(clk),
.reset(reset),

30
lab2CA.xpr
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@@ -94,6 +94,20 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/dataMemory.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/instructionMemory.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/CPU9bits.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@@ -109,22 +123,6 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/instructionMemory.v">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/dataMemory.v">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="CPU9bits"/>