Added memories to the CPU

lab2CA.srcs/sources_1/new/CPU9bits.v

@@ -1,16 +1,29 @@
 `timescale 1ns / 1ps
 
 module CPU9bits(
-    input wire [8:0] instr,
     input wire reset, clk,
     output wire done
     );
     
-    wire [8:0] op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut, linkData, SE1N, SE2N, SE3N;
+    wire [8:0] instr, op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut, linkData, SE1N, SE2N, SE3N;
     wire [2:0] FU;
     wire [3:0] aluOp;
     wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1, link;
         
+    instructionMemory iM(
+        .clk(clk),
+        .address(PCout),
+        .readData(instr)
+        );
+    
+    dataMemory dM(
+        .clk(clk),
+        .writeEnable(loadS),
+        .writeData(op0),
+        .address(AluOut),
+        .readData(dataMemOut)
+        );    
+          
     RegFile RF(
         .clk(clk),
         .reset(reset),