William/WMU-ECE-3570-Lab
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Idek what ive changed its been so long

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Johannes
2019-04-11 21:54:34 -04:00
parent a3064a836b
commit fa5e1d2739
46 changed files with 560 additions and 1015 deletions
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lab2CA.runs/impl_1/CPU9bits.tcl
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@@ -68,7 +68,6 @@ start_step init_design
set ACTIVE_STEP init_design
set rc [catch {
create_msg_db init_design.pb
set_param synth.incrementalSynthesisCache C:/Users/ecelab/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-3864-DESKTOP-8QFGS52/incrSyn
create_project -in_memory -part xc7k160tifbg484-2L
set_property design_mode GateLvl [current_fileset]
set_param project.singleFileAddWarning.threshold 0