William/WMU-ECE-3570-Lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Idek what ive changed its been so long

Browse Source
This commit is contained in:
Johannes
2019-04-11 21:54:34 -04:00
parent a3064a836b
commit fa5e1d2739
46 changed files with 560 additions and 1015 deletions
Download Patch File Download Diff File Expand all files Collapse all files

37
lab2CA.runs/impl_1/CPU9bits_control_sets_placed.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Thu Apr 11 18:42:32 2019
| Date : Thu Apr 11 19:41:43 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt
| Design : CPU9bits
@@ -23,8 +23,8 @@ Table of Contents
+----------------------------------------------------------+-------+
| Status | Count |
+----------------------------------------------------------+-------+
| Number of unique control sets | 9 |
| Unused register locations in slices containing registers | 61 |
| Number of unique control sets | 4 |
| Unused register locations in slices containing registers | 27 |
+----------------------------------------------------------+-------+
@@ -34,8 +34,8 @@ Table of Contents
+--------+--------------+
| Fanout | Control Sets |
+--------+--------------+
| 9 | 8 |
| 16+ | 1 |
| 9 | 2 |
| 16+ | 2 |
+--------+--------------+
@@ -45,30 +45,25 @@ Table of Contents
+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No | No | No | 0 | 0 |
| No | No | No | 9 | 3 |
| No | No | Yes | 0 | 0 |
| No | Yes | No | 91 | 35 |
| No | Yes | No | 34 | 15 |
| Yes | No | No | 0 | 0 |
| Yes | No | Yes | 0 | 0 |
| Yes | Yes | No | 72 | 23 |
| Yes | Yes | No | 18 | 9 |
+--------------+-----------------------+------------------------+-----------------+--------------+
4. Detailed Control Set Information
-----------------------------------
+----------------+-------------------------+------------------+------------------+----------------+
| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count |
+----------------+-------------------------+------------------+------------------+----------------+
| clk_IBUF_BUFG | pipe2/Dout_reg[6]_2[0] | reset_IBUF | 5 | 9 |
| clk_IBUF_BUFG | pipe2/Dout_reg[6]_1[0] | reset_IBUF | 2 | 9 |
| clk_IBUF_BUFG | pipe2/E[0] | reset_IBUF | 2 | 9 |
| clk_IBUF_BUFG | pipe2/Dout_reg[6]_3[0] | reset_IBUF | 4 | 9 |
| clk_IBUF_BUFG | pipe1/Dout_reg[43]_0[0] | reset_IBUF | 2 | 9 |
| clk_IBUF_BUFG | pipe1/Dout_reg[1]_0[0] | reset_IBUF | 2 | 9 |
| clk_IBUF_BUFG | pipe1/Dout_reg[1]_1[0] | reset_IBUF | 2 | 9 |
| clk_IBUF_BUFG | pipe1/E[0] | reset_IBUF | 4 | 9 |
| clk_IBUF_BUFG | | reset_IBUF | 35 | 91 |
+----------------+-------------------------+------------------+------------------+----------------+
+----------------+------------------------+------------------+------------------+----------------+
| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count |
+----------------+------------------------+------------------+------------------+----------------+
| clk_IBUF_BUFG | pipe2/Dout_reg[5]_1[0] | reset_IBUF | 4 | 9 |
| clk_IBUF_BUFG | pipe2/E[0] | reset_IBUF | 5 | 9 |
| clk_IBUF_BUFG | | | 3 | 18 |
| clk_IBUF_BUFG | | reset_IBUF | 15 | 34 |
+----------------+------------------------+------------------+------------------+----------------+