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Idek what ive changed its been so long

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Johannes
2019-04-11 21:54:34 -04:00
parent a3064a836b
commit fa5e1d2739
46 changed files with 560 additions and 1015 deletions
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8
lab2CA.runs/impl_1/CPU9bits_timing_summary_routed.rpt
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@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Thu Apr 11 18:43:05 2019
| Date : Thu Apr 11 19:42:15 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation
| Design : CPU9bits
@@ -52,7 +52,7 @@ Table of Contents
1. checking no_clock
--------------------
There are 164 register/latch pins with no clock driven by root clock pin: clk (HIGH)
There are 70 register/latch pins with no clock driven by root clock pin: clk (HIGH)
2. checking constant_clock
@@ -67,7 +67,7 @@ Table of Contents
4. checking unconstrained_internal_endpoints
--------------------------------------------
There are 417 pins that are not constrained for maximum delay. (HIGH)
There are 148 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
@@ -81,7 +81,7 @@ Table of Contents
6. checking no_output_delay
---------------------------
There are 10 ports with no output delay specified. (HIGH)
There are 9 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint