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Idek what ive changed its been so long

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Johannes
2019-04-11 21:54:34 -04:00
parent a3064a836b
commit fa5e1d2739
46 changed files with 560 additions and 1015 deletions
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lab2CA.runs/impl_1/CPU9bits_utilization_placed.rpt
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@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Thu Apr 11 18:42:32 2019
| Date : Thu Apr 11 19:41:43 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb
| Design : CPU9bits
@@ -28,18 +28,20 @@ Table of Contents
1. Slice Logic
--------------
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs | 184 | 0 | 101400 | 0.18 |
| LUT as Logic | 184 | 0 | 101400 | 0.18 |
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
| Slice Registers | 163 | 0 | 202800 | 0.08 |
| Register as Flip Flop | 163 | 0 | 202800 | 0.08 |
| Register as Latch | 0 | 0 | 202800 | 0.00 |
| F7 Muxes | 3 | 0 | 50700 | <0.01 |
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
+-------------------------+------+-------+-----------+-------+
+----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+------+-------+-----------+-------+
| Slice LUTs | 92 | 0 | 101400 | 0.09 |
| LUT as Logic | 83 | 0 | 101400 | 0.08 |
| LUT as Memory | 9 | 0 | 35000 | 0.03 |
| LUT as Distributed RAM | 9 | 0 | | |
| LUT as Shift Register | 0 | 0 | | |
| Slice Registers | 61 | 0 | 202800 | 0.03 |
| Register as Flip Flop | 61 | 0 | 202800 | 0.03 |
| Register as Latch | 0 | 0 | 202800 | 0.00 |
| F7 Muxes | 1 | 0 | 50700 | <0.01 |
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
+----------------------------+------+-------+-----------+-------+
1.1 Summary of Registers by Type
@@ -57,7 +59,7 @@ Table of Contents
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 163 | Yes | Reset | - |
| 61 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
@@ -67,22 +69,25 @@ Table of Contents
+--------------------------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+--------------------------------------------+------+-------+-----------+-------+
| Slice | 65 | 0 | 25350 | 0.26 |
| SLICEL | 44 | 0 | | |
| SLICEM | 21 | 0 | | |
| LUT as Logic | 184 | 0 | 101400 | 0.18 |
| Slice | 28 | 0 | 25350 | 0.11 |
| SLICEL | 21 | 0 | | |
| SLICEM | 7 | 0 | | |
| LUT as Logic | 83 | 0 | 101400 | 0.08 |
| using O5 output only | 0 | | | |
| using O6 output only | 144 | | | |
| using O5 and O6 | 40 | | | |
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | | |
| using O6 output only | 70 | | | |
| using O5 and O6 | 13 | | | |
| LUT as Memory | 9 | 0 | 35000 | 0.03 |
| LUT as Distributed RAM | 9 | 0 | | |
| using O5 output only | 0 | | | |
| using O6 output only | 9 | | | |
| using O5 and O6 | 0 | | | |
| LUT as Shift Register | 0 | 0 | | |
| Slice Registers | 163 | 0 | 202800 | 0.08 |
| Register driven from within the Slice | 68 | | | |
| Register driven from outside the Slice | 95 | | | |
| LUT in front of the register is unused | 46 | | | |
| LUT in front of the register is used | 49 | | | |
| Unique Control Sets | 9 | | 25350 | 0.04 |
| Slice Registers | 61 | 0 | 202800 | 0.03 |
| Register driven from within the Slice | 30 | | | |
| Register driven from outside the Slice | 31 | | | |
| LUT in front of the register is unused | 3 | | | |
| LUT in front of the register is used | 28 | | | |
| Unique Control Sets | 4 | | 25350 | 0.02 |
+--------------------------------------------+------+-------+-----------+-------+
* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets.
@@ -90,14 +95,13 @@ Table of Contents
3. Memory
---------
+-------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile | 0.5 | 0 | 325 | 0.15 |
| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 |
| RAMB18 | 1 | 0 | 650 | 0.15 |
| RAMB18E1 only | 1 | | | |
+-------------------+------+-------+-----------+-------+
+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| Block RAM Tile | 0 | 0 | 325 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 |
| RAMB18 | 0 | 0 | 650 | 0.00 |
+----------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
@@ -180,17 +184,16 @@ Table of Contents
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDRE | 163 | Flop & Latch |
| LUT6 | 93 | LUT |
| LUT5 | 52 | LUT |
| LUT3 | 36 | LUT |
| LUT4 | 34 | LUT |
| FDRE | 61 | Flop & Latch |
| LUT6 | 47 | LUT |
| LUT3 | 19 | LUT |
| LUT4 | 14 | LUT |
| LUT5 | 11 | LUT |
| OBUF | 10 | IO |
| LUT2 | 8 | LUT |
| MUXF7 | 3 | MuxFx |
| RAMS32 | 9 | Distributed Memory |
| LUT2 | 5 | LUT |
| IBUF | 2 | IO |
| RAMB18E1 | 1 | Block Memory |
| LUT1 | 1 | LUT |
| MUXF7 | 1 | MuxFx |
| BUFG | 1 | Clock |
+----------+------+---------------------+