Idek what ive changed its been so long
This commit is contained in:
Johannes
@@ -2,8 +2,8 @@
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# Vivado v2018.3 (64-bit)
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# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
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# Start of session at: Thu Apr 11 18:41:11 2019
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# Process ID: 10636
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# Start of session at: Thu Apr 11 19:40:31 2019
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# Process ID: 1252
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# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1
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# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
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# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds
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@@ -15,9 +15,9 @@ Starting synth_design
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Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti'
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INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti'
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INFO: Launching helper process for spawning children vivado processes
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INFO: Helper process launched with PID 2264
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INFO: Helper process launched with PID 12536
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---------------------------------------------------------------------------------
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Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 359.680 ; gain = 101.758
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Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 360.711 ; gain = 100.867
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---------------------------------------------------------------------------------
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INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
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INFO: [Synth 8-6157] synthesizing module 'FDModule' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FDModule.v:3]
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@@ -93,26 +93,33 @@ INFO: [Synth 8-6155] done synthesizing module 'sign_extend_2bit' (32#1) [C:/User
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INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (33#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
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WARNING: [Synth 8-3331] design dataMemory has unconnected port address[8]
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WARNING: [Synth 8-3331] design dataMemory has unconnected port address[7]
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WARNING: [Synth 8-3331] design dataMemory has unconnected port address[6]
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WARNING: [Synth 8-3331] design dataMemory has unconnected port address[5]
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WARNING: [Synth 8-3331] design dataMemory has unconnected port address[4]
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WARNING: [Synth 8-3331] design dataMemory has unconnected port address[3]
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WARNING: [Synth 8-3331] design dataMemory has unconnected port address[2]
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WARNING: [Synth 8-3331] design dataMemory has unconnected port address[1]
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WARNING: [Synth 8-3331] design EMModule has unconnected port PipIn[50]
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WARNING: [Synth 8-3331] design EMModule has unconnected port PipIn[49]
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WARNING: [Synth 8-3331] design EMModule has unconnected port PipIn[48]
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WARNING: [Synth 8-3331] design EMModule has unconnected port PipIn[47]
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---------------------------------------------------------------------------------
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Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.672 ; gain = 157.750
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Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 416.168 ; gain = 156.324
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.672 ; gain = 157.750
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Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 416.168 ; gain = 156.324
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Loading Part and Timing Information
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---------------------------------------------------------------------------------
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Loading part: xc7k160tifbg484-2L
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---------------------------------------------------------------------------------
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.672 ; gain = 157.750
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 416.168 ; gain = 156.324
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---------------------------------------------------------------------------------
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INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
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INFO: [Synth 8-5544] ROM "memory" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
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---------------------------------------------------------------------------------
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Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 415.672 ; gain = 157.750
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Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 416.168 ; gain = 156.324
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---------------------------------------------------------------------------------
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INFO: [Synth 8-223] decloning instance 'EM/SE1' (sign_extend_3bit) to 'EM/SE3'
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@@ -133,8 +140,9 @@ Detailed RTL Component Info :
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51 Bit Registers := 1
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9 Bit Registers := 10
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+---RAMs :
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909 Bit RAMs := 1
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18 Bit RAMs := 1
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+---Muxes :
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7 Input 9 Bit Muxes := 1
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2 Input 9 Bit Muxes := 10
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4 Input 9 Bit Muxes := 4
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2 Input 4 Bit Muxes := 2
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@@ -152,6 +160,10 @@ Finished RTL Component Statistics
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Start RTL Hierarchical Component Statistics
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---------------------------------------------------------------------------------
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Hierarchical RTL Component report
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Module instructionMemory
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Detailed RTL Component Info :
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+---Muxes :
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7 Input 9 Bit Muxes := 1
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Module register
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Detailed RTL Component Info :
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+---Registers :
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@@ -190,7 +202,7 @@ Detailed RTL Component Info :
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+---Registers :
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9 Bit Registers := 1
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+---RAMs :
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909 Bit RAMs := 1
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18 Bit RAMs := 1
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Module bit1_mux_2_1
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Detailed RTL Component Info :
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+---Muxes :
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@@ -216,30 +228,37 @@ No constraint files found.
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Start Cross Boundary and Area Optimization
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---------------------------------------------------------------------------------
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Warning: Parallel synthesis criteria is not met
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INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[46]' (FDRE) to 'pipe1/Dout_reg[44]'
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INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[50]' (FDRE) to 'pipe1/Dout_reg[17]'
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INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[48]' (FDRE) to 'pipe1/Dout_reg[17]'
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INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[42]' (FDRE) to 'pipe1/Dout_reg[44]'
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INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[44]' (FDRE) to 'pipe1/Dout_reg[0]'
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INFO: [Synth 8-3886] merging instance 'pipe2/Dout_reg[6]' (FDRE) to 'pipe2/Dout_reg[4]'
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INFO: [Synth 8-3333] propagating constant 0 across sequential element (\pipe1/Dout_reg[0] )
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INFO: [Synth 8-3886] merging instance 'pipe2/Dout_reg[4]' (FDRE) to 'pipe1/Dout_reg[0]'
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INFO: [Synth 8-3333] propagating constant 0 across sequential element (\pipe1/Dout_reg[0] )
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INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[4]' (FDRE) to 'pipe1/Dout_reg[14]'
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INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[9]' (FDRE) to 'pipe1/Dout_reg[14]'
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INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[14]' (FDRE) to 'pipe1/Dout_reg[11]'
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INFO: [Synth 8-3333] propagating constant 0 across sequential element (\pipe1/Dout_reg[11] )
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INFO: [Synth 8-3886] merging instance 'pipe2/Dout_reg[1]' (FDRE) to 'pipe2/Dout_reg[2]'
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INFO: [Synth 8-3886] merging instance 'pipe2/Dout_reg[2]' (FDRE) to 'pipe1/Dout_reg[11]'
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INFO: [Synth 8-3333] propagating constant 0 across sequential element (\pipe1/Dout_reg[11] )
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---------------------------------------------------------------------------------
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Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 644.680 ; gain = 386.758
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Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 622.676 ; gain = 362.832
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start ROM, RAM, DSP and Shift Register Reporting
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---------------------------------------------------------------------------------
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ROM:
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+------------------+------------+---------------+----------------+
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|Module Name | RTL Object | Depth x Width | Implemented As |
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+------------------+------------+---------------+----------------+
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|instructionMemory | p_0_out | 64x9 | LUT |
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|CPU9bits | p_0_out | 64x9 | LUT |
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+------------------+------------+---------------+----------------+
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Distributed RAM: Preliminary Mapping Report (see note below)
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+------------+------------------+-----------+----------------------+----------------+
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|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
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+------------+------------------+-----------+----------------------+----------------+
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|CPU9bits | EM/dM/memory_reg | Implied | 2 x 9 | RAM16X1S x 9 |
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+------------+------------------+-----------+----------------------+----------------+
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Block RAM: Preliminary Mapping Report (see note below)
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+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
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|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
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+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
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|dataMemory: | memory_reg | 128 x 9(NO_CHANGE) | W | R | | | | Port A | 1 | 0 |
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+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
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Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.
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Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
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---------------------------------------------------------------------------------
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Finished ROM, RAM, DSP and Shift Register Reporting
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---------------------------------------------------------------------------------
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@@ -254,18 +273,18 @@ No constraint files found.
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Start Timing Optimization
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 644.680 ; gain = 386.758
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Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 622.676 ; gain = 362.832
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start ROM, RAM, DSP and Shift Register Reporting
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---------------------------------------------------------------------------------
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Block RAM: Final Mapping Report
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+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
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|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
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+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
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|dataMemory: | memory_reg | 128 x 9(NO_CHANGE) | W | R | | | | Port A | 1 | 0 |
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+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
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Distributed RAM: Final Mapping Report
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+------------+------------------+-----------+----------------------+----------------+
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|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
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+------------+------------------+-----------+----------------------+----------------+
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|CPU9bits | EM/dM/memory_reg | Implied | 2 x 9 | RAM16X1S x 9 |
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+------------+------------------+-----------+----------------------+----------------+
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---------------------------------------------------------------------------------
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Finished ROM, RAM, DSP and Shift Register Reporting
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@@ -279,8 +298,13 @@ Report RTL Partitions:
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---------------------------------------------------------------------------------
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Start Technology Mapping
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---------------------------------------------------------------------------------
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INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[10]' (FDRE) to 'pipe1/Dout_reg[3]'
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INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[17]' (FDRE) to 'pipe1/Dout_reg[5]'
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INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[3]' (FDRE) to 'pipe1/Dout_reg[6]'
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INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[8]' (FDRE) to 'pipe1/Dout_reg[6]'
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INFO: [Synth 8-3333] propagating constant 0 across sequential element (\pipe1/Dout_reg[6] )
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---------------------------------------------------------------------------------
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Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 644.680 ; gain = 386.758
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Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 622.676 ; gain = 362.832
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---------------------------------------------------------------------------------
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Report RTL Partitions:
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@@ -304,7 +328,7 @@ Start Final Netlist Cleanup
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Finished Final Netlist Cleanup
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 644.680 ; gain = 386.758
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Finished IO Insertion : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 622.676 ; gain = 362.832
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---------------------------------------------------------------------------------
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Report Check Netlist:
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@@ -317,7 +341,7 @@ Report Check Netlist:
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Start Renaming Generated Instances
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 644.680 ; gain = 386.758
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Finished Renaming Generated Instances : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 622.676 ; gain = 362.832
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---------------------------------------------------------------------------------
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Report RTL Partitions:
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@@ -329,25 +353,25 @@ Report RTL Partitions:
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Start Rebuilding User Hierarchy
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 644.680 ; gain = 386.758
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Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 622.676 ; gain = 362.832
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Renaming Generated Ports
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 644.680 ; gain = 386.758
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Finished Renaming Generated Ports : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 622.676 ; gain = 362.832
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Handling Custom Attributes
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 644.680 ; gain = 386.758
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 622.676 ; gain = 362.832
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Renaming Generated Nets
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 644.680 ; gain = 386.758
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Finished Renaming Generated Nets : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 622.676 ; gain = 362.832
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Writing Synthesis Report
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@@ -364,64 +388,57 @@ Report Cell Usage:
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| |Cell |Count |
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+------+---------+------+
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|1 |BUFG | 1|
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|2 |LUT1 | 14|
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|3 |LUT2 | 8|
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|4 |LUT3 | 36|
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|5 |LUT4 | 34|
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|6 |LUT5 | 52|
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|7 |LUT6 | 93|
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|8 |MUXF7 | 3|
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|9 |RAMB18E1 | 1|
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|10 |FDRE | 163|
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|11 |IBUF | 2|
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|12 |OBUF | 10|
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|2 |LUT2 | 5|
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|3 |LUT3 | 18|
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|4 |LUT4 | 14|
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|5 |LUT5 | 11|
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|6 |LUT6 | 47|
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|7 |MUXF7 | 2|
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|8 |RAM16X1S | 9|
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|9 |FDRE | 61|
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|10 |IBUF | 2|
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|11 |OBUF | 10|
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+------+---------+------+
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Report Instance Areas:
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+------+-----------+-----------+------+
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| |Instance |Module |Cells |
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+------+-----------+-----------+------+
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|1 |top | | 417|
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|2 | EM |EMModule | 46|
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||||
|3 | Bank |RegFile_4 | 45|
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||||
|4 | r0 |register_5 | 17|
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||||
|5 | r1 |register_6 | 10|
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||||
|6 | r2 |register_7 | 9|
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||||
|7 | r3 |register_8 | 9|
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||||
|8 | dM |dataMemory | 1|
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||||
|9 | FD |FDModule | 207|
|
||||
|10 | FetchU |FetchUnit | 131|
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||||
|11 | PC |register_3 | 131|
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||||
|12 | RF |RegFile | 76|
|
||||
|13 | r0 |register | 18|
|
||||
|14 | r1 |register_0 | 31|
|
||||
|15 | r2 |register_1 | 18|
|
||||
|16 | r3 |register_2 | 9|
|
||||
|17 | pipe1 |fDPipReg | 73|
|
||||
|18 | pipe2 |eMPipReg | 78|
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||||
|1 |top | | 180|
|
||||
|2 | EM |EMModule | 18|
|
||||
|3 | dM |dataMemory | 18|
|
||||
|4 | FD |FDModule | 106|
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||||
|5 | FetchU |FetchUnit | 82|
|
||||
|6 | PC |register_1 | 82|
|
||||
|7 | RF |RegFile | 24|
|
||||
|8 | r0 |register | 11|
|
||||
|9 | r1 |register_0 | 13|
|
||||
|10 | pipe1 |fDPipReg | 7|
|
||||
|11 | pipe2 |eMPipReg | 36|
|
||||
+------+-----------+-----------+------+
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||||
---------------------------------------------------------------------------------
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||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 644.680 ; gain = 386.758
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 622.676 ; gain = 362.832
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 6 warnings.
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||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 644.680 ; gain = 386.758
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 644.680 ; gain = 386.758
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 12 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 622.676 ; gain = 362.832
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 622.676 ; gain = 362.832
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
|
||||
INFO: [Netlist 29-17] Analyzing 11 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 681.133 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 682.727 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
A total of 9 instances were transformed.
|
||||
RAM16X1S => RAM32X1S (RAMS32): 9 instances
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
82 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
104 Infos, 12 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:26 . Memory (MB): peak = 681.133 ; gain = 425.672
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 681.133 ; gain = 0.000
|
||||
synth_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:24 . Memory (MB): peak = 682.727 ; gain = 422.883
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 682.727 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Thu Apr 11 18:41:41 2019...
|
||||
INFO: [Common 17-206] Exiting Vivado at Thu Apr 11 19:40:59 2019...
|
||||
|
||||
Reference in New Issue
Block a user