Idek what ive changed its been so long

lab2CA.srcs/sources_1/new/CPU9bits.v

@@ -154,7 +154,7 @@ module CPU9bits_tb();
     	reset = 1'b1;
     	#10
     	reset = 1'b0;
-    	#300
+    	#100
         $finish;
         
     end

lab2CA.srcs/sources_1/new/EMModule.v

@@ -1,7 +1,5 @@
 `timescale 1ns / 1ps
 
-
-
 module EMModule(
     input wire reset, clk,
     input wire [50:0] PipIn,

lab2CA.srcs/sources_1/new/WMUdule.v

@@ -56,3 +56,26 @@ module WMUdule(
         .switch(link)
     );
 endmodule
+
+//module WMUdule_tb();
+//    reg [61:0] PipIn;
+//    wire [8:0] RFIn,FUAddr;
+//    wire [1:0] instr;
+//    wire fetchBranch, RegEn;
+
+//    WMUdule WMUdule_0(
+//        .PipIn(PipIn),
+//        .RFIn(RFIn),
+//        .FUAddr(FUAddr),
+//        .instr(instr),
+//        .fetchBranch(fetchBranch),
+//        .RegEn(RegEn)
+//        );
+    
+//    initial begin
+//        PipIn = 1;
+//        #5
+//        $finish;
+
+//    end
+//endmodule

lab2CA.srcs/sources_1/new/instructionMemory.v

@@ -5,7 +5,7 @@ module instructionMemory(
     output reg [8:0] readData
     );
     
-    reg [8:0] memory [5:0];   // Maximum of 512 memory locations
+    reg [8:0] memory [6:0];   // Maximum of 512 memory locations
                                 // Vivado will give warnings of unconnected ports on the "address" bus if they are unused
     
     initial begin
@@ -15,7 +15,8 @@ module instructionMemory(
         memory[2] <= 9'b000101000; //load
         memory[3] <= 9'b010100010; //add
         memory[4] <= 9'b111100000; //shift left
-        memory[5] <= 9'b111100000; //shift left
+        memory[5] <= 9'b000000001; //NOP
+        memory[6] <= 9'b111100000; //shift left
         
 //        //Testing all instructions
 //        memory[6] <= 9'b010100011; //sub