Commit Graph

19 Commits

Author SHA1 Message Date
Johannes
bc9c02322c Added forwarding 2019-04-11 18:36:00 -04:00
jose.rodriguezlabra
42d2bf2d80 Fixed pip enables, fixed Nop/Halt 2019-04-11 17:32:17 -04:00
WilliamMiceli
eaec5f0883 Vivado stuff 2019-04-10 12:51:15 -04:00
Johannes
e6cb8e536b Added Pipeline 2019-04-06 17:51:44 -04:00
WilliamMiceli
78f481f724 Vivado stuff 2019-03-29 17:29:24 -04:00
WilliamMiceli
7490815502 Making fixes to Bubble Sort 2019-03-24 19:27:59 -04:00
Johannes
03df69372a String Compare Working 2019-03-24 17:05:09 -04:00
Johannes
9a2e84bda6 metadata 2019-03-24 16:09:40 -04:00
Johannes
e8ada91e08 BEQ and LD fix 2019-03-24 16:05:16 -04:00
jose.rodriguezlabra
27f6d24b88 Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
# Conflicts:
#	lab2CA.cache/wt/webtalk_pa.xml
#	lab2CA.runs/impl_1/gen_run.xml
#	lab2CA.runs/synth_1/gen_run.xml
#	lab2CA.sim/sim_1/behav/xsim/xelab.pb
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
#	lab2CA.sim/sim_1/behav/xsim/xvlog.pb
#	lab2CA.srcs/sources_1/new/instructionMemory.v
#	lab2CA.xpr
2019-03-24 14:17:59 -04:00
Johannes
ee9e420365 Added string compare to instruction and data memory 2019-03-24 14:14:28 -04:00
jose.rodriguezlabra
bab680ea27 Added bank to CPU9bits 2019-03-24 12:11:12 -04:00
WilliamMiceli
ad6765a43a BEQ Opcode fix & other stuffz 2019-03-22 19:54:06 -04:00
Johannes
c85ad153dc Tested the instructions using the instruction memory
All of the instructions seem to be working other than beq. I might just be calling it wrong
2019-03-20 12:08:24 -04:00
jose.rodriguezlabra
eeb9c7c318 Tested zero 2019-03-16 14:55:11 -04:00
jose.rodriguezlabra
dfd8753a62 Implemented SEs 2019-03-16 14:09:53 -04:00
jose.rodriguezlabra
5cbe490aae Added link instruction 2019-03-16 14:01:32 -04:00
jose.rodriguezlabra
08e3659ba3 Better Sim 2019-03-14 14:37:58 -04:00
jose.rodriguezlabra
11a1d99e92 Computer works (kinda) 2019-03-13 12:51:44 -04:00