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Vivado stuff

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This commit is contained in:
WilliamMiceli
2019-04-10 12:51:15 -04:00
parent 616dac4d29
commit eaec5f0883
50 changed files with 306 additions and 2919 deletions
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95
lab2CA.cache/wt/webtalk_pa.xml
View File

@@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Sat Apr 6 17:51:16 2019">
<application name="pa" timeStamp="Wed Apr 10 12:50:22 2019">
<section name="Project Information" visible="false">
<property name="ProjectID" value="88e779ed22f94d2db93b335d17c75f15" type="ProjectID"/>
<property name="ProjectIteration" value="26" type="ProjectIteration"/>
@@ -18,8 +18,8 @@ This means code written to parse this file will need to be revisited each subseq
</item>
<item name="Java Command Handlers">
<property name="AddSources" value="6" type="JavaHandler"/>
<property name="CloseProject" value="20" type="JavaHandler"/>
<property name="EditDelete" value="5" type="JavaHandler"/>
<property name="CloseProject" value="21" type="JavaHandler"/>
<property name="EditDelete" value="8" type="JavaHandler"/>
<property name="FlipToViewTaskRTLAnalysis" value="1" type="JavaHandler"/>
<property name="OpenDesign" value="1" type="JavaHandler"/>
<property name="OpenFile" value="1" type="JavaHandler"/>
@@ -28,17 +28,18 @@ This means code written to parse this file will need to be revisited each subseq
<property name="ReportTimingSummary" value="9" type="JavaHandler"/>
<property name="RunImplementation" value="31" type="JavaHandler"/>
<property name="RunSchematic" value="35" type="JavaHandler"/>
<property name="RunSynthesis" value="29" type="JavaHandler"/>
<property name="RunSynthesis" value="31" type="JavaHandler"/>
<property name="SaveFileProxyHandler" value="5" type="JavaHandler"/>
<property name="SaveLayoutAs" value="1" type="JavaHandler"/>
<property name="SetSourceEnabled" value="5" type="JavaHandler"/>
<property name="SetTopNode" value="43" type="JavaHandler"/>
<property name="ShowSimulationDefaultWaveFormView" value="1" type="JavaHandler"/>
<property name="ShowSource" value="1" type="JavaHandler"/>
<property name="ShowView" value="18" type="JavaHandler"/>
<property name="ShowView" value="19" type="JavaHandler"/>
<property name="SimulationClose" value="6" type="JavaHandler"/>
<property name="SimulationRelaunch" value="98" type="JavaHandler"/>
<property name="SimulationRun" value="96" type="JavaHandler"/>
<property name="SimulationRelaunch" value="103" type="JavaHandler"/>
<property name="SimulationRun" value="97" type="JavaHandler"/>
<property name="SimulationRunForTime" value="5" type="JavaHandler"/>
<property name="TclFind" value="7" type="JavaHandler"/>
<property name="ToggleSelectAreaMode" value="3" type="JavaHandler"/>
<property name="ToggleViewNavigator" value="1" type="JavaHandler"/>
@@ -46,10 +47,10 @@ This means code written to parse this file will need to be revisited each subseq
<property name="UpdateSourceFiles" value="1" type="JavaHandler"/>
<property name="ViewLayoutCmd" value="2" type="JavaHandler"/>
<property name="ViewTaskImplementation" value="4" type="JavaHandler"/>
<property name="ViewTaskProjectManager" value="1" type="JavaHandler"/>
<property name="ViewTaskProjectManager" value="2" type="JavaHandler"/>
<property name="ViewTaskRTLAnalysis" value="16" type="JavaHandler"/>
<property name="WaveformOpenConfiguration" value="1" type="JavaHandler"/>
<property name="WaveformSaveConfiguration" value="9" type="JavaHandler"/>
<property name="WaveformOpenConfiguration" value="2" type="JavaHandler"/>
<property name="WaveformSaveConfiguration" value="13" type="JavaHandler"/>
<property name="WaveformSaveConfigurationAs" value="1" type="JavaHandler"/>
<property name="ZoomFit" value="11" type="JavaHandler"/>
<property name="ZoomOut" value="3" type="JavaHandler"/>
@@ -59,8 +60,8 @@ This means code written to parse this file will need to be revisited each subseq
<property name="AbstractSearchablePanel_SHOW_SEARCH" value="2" type="GuiHandlerData"/>
<property name="BaseDialogUtils_OPEN_IN_SPECIFIED_LAYOUT" value="1" type="GuiHandlerData"/>
<property name="BaseDialog_APPLY" value="1" type="GuiHandlerData"/>
<property name="BaseDialog_CANCEL" value="32" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="149" type="GuiHandlerData"/>
<property name="BaseDialog_CANCEL" value="33" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="151" type="GuiHandlerData"/>
<property name="BaseDialog_YES" value="21" type="GuiHandlerData"/>
<property name="ClosePlanner_YES" value="1" type="GuiHandlerData"/>
<property name="CmdMsgDialog_MESSAGES" value="2" type="GuiHandlerData"/>
@@ -68,39 +69,39 @@ This means code written to parse this file will need to be revisited each subseq
<property name="CmdMsgDialog_OPEN_MESSAGES_VIEW" value="2" type="GuiHandlerData"/>
<property name="CodeView_TOGGLE_COLUMN_SELECTION_MODE" value="14" type="GuiHandlerData"/>
<property name="CreateSrcFileDialog_FILE_NAME" value="7" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="590" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="641" type="GuiHandlerData"/>
<property name="FloatingTopDialog_SELECT_TOP_MODULE_OF_YOUR_DESIGN" value="12" type="GuiHandlerData"/>
<property name="FloatingTopDialog_SPECIFY_NEW_TOP_MODULE" value="10" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="290" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="299" type="GuiHandlerData"/>
<property name="GettingStartedView_OPEN_PROJECT" value="2" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_FIT" value="68" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_IN" value="68" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_OUT" value="57" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_IN" value="74" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_OUT" value="60" type="GuiHandlerData"/>
<property name="HCodeEditor_BLANK_OPERATIONS" value="6" type="GuiHandlerData"/>
<property name="HCodeEditor_CLOSE" value="9" type="GuiHandlerData"/>
<property name="HCodeEditor_COMMANDS_TO_FOLD_TEXT" value="3" type="GuiHandlerData"/>
<property name="HCodeEditor_DIFF_WITH" value="3" type="GuiHandlerData"/>
<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="64" type="GuiHandlerData"/>
<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="65" type="GuiHandlerData"/>
<property name="HInputHandler_INDENT_SELECTION" value="1" type="GuiHandlerData"/>
<property name="HInputHandler_TOGGLE_LINE_COMMENTS" value="15" type="GuiHandlerData"/>
<property name="HPopupTitle_CLOSE" value="1" type="GuiHandlerData"/>
<property name="InstanceMenu_FLOORPLANNING" value="2" type="GuiHandlerData"/>
<property name="LaunchPanel_DONT_SHOW_THIS_DIALOG_AGAIN" value="1" type="GuiHandlerData"/>
<property name="MainMenuMgr_CHECKPOINT" value="6" type="GuiHandlerData"/>
<property name="MainMenuMgr_CHECKPOINT" value="7" type="GuiHandlerData"/>
<property name="MainMenuMgr_CONSTRAINTS" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_EDIT" value="14" type="GuiHandlerData"/>
<property name="MainMenuMgr_EXPORT" value="5" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="66" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="70" type="GuiHandlerData"/>
<property name="MainMenuMgr_FLOW" value="8" type="GuiHandlerData"/>
<property name="MainMenuMgr_IP" value="6" type="GuiHandlerData"/>
<property name="MainMenuMgr_IP" value="7" type="GuiHandlerData"/>
<property name="MainMenuMgr_OPEN_BLOCK_DESIGN" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="31" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="32" type="GuiHandlerData"/>
<property name="MainMenuMgr_REPORTS" value="4" type="GuiHandlerData"/>
<property name="MainMenuMgr_RUN" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_SETTINGS" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_SIMULATION_WAVEFORM" value="13" type="GuiHandlerData"/>
<property name="MainMenuMgr_TEXT_EDITOR" value="7" type="GuiHandlerData"/>
<property name="MainMenuMgr_SIMULATION_WAVEFORM" value="16" type="GuiHandlerData"/>
<property name="MainMenuMgr_TEXT_EDITOR" value="8" type="GuiHandlerData"/>
<property name="MainMenuMgr_TOOLS" value="6" type="GuiHandlerData"/>
<property name="MainMenuMgr_VIEW" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_WINDOW" value="8" type="GuiHandlerData"/>
@@ -108,8 +109,10 @@ This means code written to parse this file will need to be revisited each subseq
<property name="MainWinMenuMgr_LAYOUT" value="4" type="GuiHandlerData"/>
<property name="MainWinToolbarMgr_SELECT_OR_SAVE_WINDOW_LAYOUT" value="3" type="GuiHandlerData"/>
<property name="MessageWithOptionDialog_DONT_SHOW_THIS_DIALOG_AGAIN" value="6" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_SEVERITY" value="2" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="160" type="GuiHandlerData"/>
<property name="MsgTreePanel_DISCARD_USER_CREATED_MESSAGES" value="2" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_SEVERITY" value="5" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="175" type="GuiHandlerData"/>
<property name="MsgTreePanel_SUPPRESS_THIS_MESSAGE" value="1" type="GuiHandlerData"/>
<property name="MsgView_CLEAR_MESSAGES_RESULTING_FROM_USER_EXECUTED" value="5" type="GuiHandlerData"/>
<property name="MsgView_INFORMATION_MESSAGES" value="1" type="GuiHandlerData"/>
<property name="MsgView_WARNING_MESSAGES" value="3" type="GuiHandlerData"/>
@@ -118,11 +121,11 @@ This means code written to parse this file will need to be revisited each subseq
<property name="NetlistSchMenuAndMouse_VIEW" value="2" type="GuiHandlerData"/>
<property name="NetlistSchematicView_SHOW_IO_PORTS_IN_THIS_SCHEMATIC" value="1" type="GuiHandlerData"/>
<property name="NetlistTreeView_NETLIST_TREE" value="4" type="GuiHandlerData"/>
<property name="OpenFileAction_CANCEL" value="2" type="GuiHandlerData"/>
<property name="OpenFileAction_CANCEL" value="3" type="GuiHandlerData"/>
<property name="OpenFileAction_OK" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_ADD_SOURCES" value="6" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_UPDATE_HIER" value="52" type="GuiHandlerData"/>
<property name="PACommandNames_CLOSE_PROJECT" value="19" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_UPDATE_HIER" value="55" type="GuiHandlerData"/>
<property name="PACommandNames_CLOSE_PROJECT" value="20" type="GuiHandlerData"/>
<property name="PACommandNames_GOTO_INSTANTIATION" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_MESSAGE_WINDOW" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_OPEN_PROJECT" value="1" type="GuiHandlerData"/>
@@ -133,9 +136,10 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PACommandNames_SET_AS_TOP" value="44" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_CLOSE" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_DEFAULT_WAVEFORM_WINDOW" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RELAUNCH" value="107" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_LIVE_RUN" value="5" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RELAUNCH" value="112" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="95" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="96" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_POST_IMPLEMENTATION_FUNCTIONAL" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_POST_IMPLEMENTATION_TIMING" value="4" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_SETTINGS" value="2" type="GuiHandlerData"/>
@@ -145,10 +149,10 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PACommandNames_TOGGLE_VIEW_NAV" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_ZOOM_FIT" value="11" type="GuiHandlerData"/>
<property name="PACommandNames_ZOOM_OUT" value="3" type="GuiHandlerData"/>
<property name="PAViews_CODE" value="54" type="GuiHandlerData"/>
<property name="PAViews_CODE" value="58" type="GuiHandlerData"/>
<property name="PAViews_DEVICE" value="3" type="GuiHandlerData"/>
<property name="PAViews_PATH_TABLE" value="1" type="GuiHandlerData"/>
<property name="PAViews_PROJECT_SUMMARY" value="66" type="GuiHandlerData"/>
<property name="PAViews_PROJECT_SUMMARY" value="67" type="GuiHandlerData"/>
<property name="PAViews_SCHEMATIC" value="33" type="GuiHandlerData"/>
<property name="PathReportTableView_DESCRIPTION" value="2" type="GuiHandlerData"/>
<property name="PlanAheadTab_SHOW_FLOW_NAVIGATOR" value="2" type="GuiHandlerData"/>
@@ -159,48 +163,49 @@ This means code written to parse this file will need to be revisited each subseq
<property name="ProjectSettingsSimulationPanel_TABBED_PANE" value="2" type="GuiHandlerData"/>
<property name="ProjectTab_RELOAD" value="30" type="GuiHandlerData"/>
<property name="RDICommands_COPY" value="2" type="GuiHandlerData"/>
<property name="RDICommands_DELETE" value="4" type="GuiHandlerData"/>
<property name="RDICommands_DELETE" value="6" type="GuiHandlerData"/>
<property name="RDICommands_LINE_COMMENT" value="2" type="GuiHandlerData"/>
<property name="RDICommands_REDO" value="1" type="GuiHandlerData"/>
<property name="RDICommands_SAVE_FILE" value="147" type="GuiHandlerData"/>
<property name="RDICommands_WAVEFORM_OPEN_CONFIGURATION" value="1" type="GuiHandlerData"/>
<property name="RDICommands_WAVEFORM_SAVE_CONFIGURATION" value="5" type="GuiHandlerData"/>
<property name="RDICommands_SAVE_FILE" value="148" type="GuiHandlerData"/>
<property name="RDICommands_WAVEFORM_OPEN_CONFIGURATION" value="2" type="GuiHandlerData"/>
<property name="RDICommands_WAVEFORM_SAVE_CONFIGURATION" value="9" type="GuiHandlerData"/>
<property name="RDICommands_WAVEFORM_SAVE_CONFIGURATION_AS" value="1" type="GuiHandlerData"/>
<property name="RDIViews_WAVEFORM_VIEWER" value="895" type="GuiHandlerData"/>
<property name="RDIViews_WAVEFORM_VIEWER" value="914" type="GuiHandlerData"/>
<property name="ReportTimingSummaryDialog_REPORT_TIMING_SUMMARY_DIALOG_TABBED" value="14" type="GuiHandlerData"/>
<property name="ReportTimingSummaryDialog_REPORT_UNCONSTRAINED_PATHS" value="6" type="GuiHandlerData"/>
<property name="RunGadget_SHOW_ERROR" value="1" type="GuiHandlerData"/>
<property name="RunGadget_SHOW_WARNING_AND_ERROR_MESSAGES_IN_MESSAGES" value="4" type="GuiHandlerData"/>
<property name="RunGadget_SHOW_WARNING_AND_ERROR_MESSAGES_IN_MESSAGES" value="5" type="GuiHandlerData"/>
<property name="SaveProjectUtils_CANCEL" value="1" type="GuiHandlerData"/>
<property name="SaveProjectUtils_SAVE" value="12" type="GuiHandlerData"/>
<property name="SelectMenu_HIGHLIGHT" value="2" type="GuiHandlerData"/>
<property name="SelectMenu_MARK" value="2" type="GuiHandlerData"/>
<property name="SelectTopModuleDialog_SELECT_TOP_MODULE" value="12" type="GuiHandlerData"/>
<property name="SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE" value="83" type="GuiHandlerData"/>
<property name="SimulationScopesPanel_SIMULATE_SCOPE_TABLE" value="140" type="GuiHandlerData"/>
<property name="SimulationScopesPanel_SIMULATE_SCOPE_TABLE" value="166" type="GuiHandlerData"/>
<property name="SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT" value="1" type="GuiHandlerData"/>
<property name="SrcChooserPanel_CREATE_FILE" value="5" type="GuiHandlerData"/>
<property name="SrcMenu_IP_HIERARCHY" value="51" type="GuiHandlerData"/>
<property name="SrcMenu_IP_HIERARCHY" value="55" type="GuiHandlerData"/>
<property name="StaleMoreAction_OUT_OF_DATE_DETAILS" value="1" type="GuiHandlerData"/>
<property name="StaleRunDialog_NO" value="3" type="GuiHandlerData"/>
<property name="StaleRunDialog_YES" value="1" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="31" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="32" type="GuiHandlerData"/>
<property name="SyntheticaStateMonitor_CANCEL" value="2" type="GuiHandlerData"/>
<property name="TaskBanner_CLOSE" value="41" type="GuiHandlerData"/>
<property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="1" type="GuiHandlerData"/>
<property name="TclFindDialog_RESULT_NAME" value="2" type="GuiHandlerData"/>
<property name="TimingDialogUtils_RESULTS_NAME" value="1" type="GuiHandlerData"/>
<property name="TimingItemFlatTablePanel_TABLE" value="3" type="GuiHandlerData"/>
<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="491" type="GuiHandlerData"/>
<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="588" type="GuiHandlerData"/>
<property name="WaveformView_GOTO_CURSOR" value="3" type="GuiHandlerData"/>
<property name="WaveformView_GOTO_LAST_TIME" value="1" type="GuiHandlerData"/>
<property name="WaveformView_GOTO_TIME_0" value="8" type="GuiHandlerData"/>
<property name="WaveformView_GOTO_TIME_0" value="9" type="GuiHandlerData"/>
<property name="WaveformView_PREVIOUS_MARKER" value="1" type="GuiHandlerData"/>
<property name="WaveformView_PREVIOUS_TRANSITION" value="2" type="GuiHandlerData"/>
</item>
<item name="Other">
<property name="GuiMode" value="19" type="GuiMode"/>
<property name="GuiMode" value="73" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="17" type="TclMode"/>
<property name="TclMode" value="70" type="TclMode"/>
</item>
</section>
</application>

8
lab2CA.runs/.jobs/vrs_config_71.xml Normal file
View File

@@ -0,0 +1,8 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

8
lab2CA.runs/.jobs/vrs_config_72.xml Normal file
View File

@@ -0,0 +1,8 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

153
lab2CA.runs/impl_1/CPU9bits.tcl
View File

@@ -1,153 +0,0 @@
#
# Report generation script generated by Vivado
#
proc create_report { reportName command } {
set status "."
append status $reportName ".fail"
if { [file exists $status] } {
eval file delete [glob $status]
}
send_msg_id runtcl-4 info "Executing : $command"
set retval [eval catch { $command } msg]
if { $retval != 0 } {
set fp [open $status w]
close $fp
send_msg_id runtcl-5 warning "$msg"
}
}
proc start_step { step } {
set stopFile ".stop.rst"
if {[file isfile .stop.rst]} {
puts ""
puts "*** Halting run - EA reset detected ***"
puts ""
puts ""
return -code error
}
set beginFile ".$step.begin.rst"
set platform "$::tcl_platform(platform)"
set user "$::tcl_platform(user)"
set pid [pid]
set host ""
if { [string equal $platform unix] } {
if { [info exist ::env(HOSTNAME)] } {
set host $::env(HOSTNAME)
}
} else {
if { [info exist ::env(COMPUTERNAME)] } {
set host $::env(COMPUTERNAME)
}
}
set ch [open $beginFile w]
puts $ch "<?xml version=\"1.0\"?>"
puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
puts $ch " </Process>"
puts $ch "</ProcessHandle>"
close $ch
}
proc end_step { step } {
set endFile ".$step.end.rst"
set ch [open $endFile w]
close $ch
}
proc step_failed { step } {
set endFile ".$step.error.rst"
set ch [open $endFile w]
close $ch
}
set_msg_config -id {Synth 8-256} -limit 10000
set_msg_config -id {Synth 8-638} -limit 10000
start_step init_design
set ACTIVE_STEP init_design
set rc [catch {
create_msg_db init_design.pb
set_param synth.incrementalSynthesisCache C:/Users/ecelab/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-10176-DESKTOP-8QFGS52/incrSyn
create_project -in_memory -part xc7k160tifbg484-2L
set_property design_mode GateLvl [current_fileset]
set_param project.singleFileAddWarning.threshold 0
set_property webtalk.parent_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.cache/wt [current_project]
set_property parent.project_path C:/Users/ecelab/ECE3570-Lab/lab2CA.xpr [current_project]
set_property ip_output_repo C:/Users/ecelab/ECE3570-Lab/lab2CA.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
add_files -quiet C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.dcp
link_design -top CPU9bits -part xc7k160tifbg484-2L
close_msg_db -file init_design.pb
} RESULT]
if {$rc} {
step_failed init_design
return -code error $RESULT
} else {
end_step init_design
unset ACTIVE_STEP
}
start_step opt_design
set ACTIVE_STEP opt_design
set rc [catch {
create_msg_db opt_design.pb
opt_design
write_checkpoint -force CPU9bits_opt.dcp
create_report "impl_1_opt_report_drc_0" "report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx"
close_msg_db -file opt_design.pb
} RESULT]
if {$rc} {
step_failed opt_design
return -code error $RESULT
} else {
end_step opt_design
unset ACTIVE_STEP
}
start_step place_design
set ACTIVE_STEP place_design
set rc [catch {
create_msg_db place_design.pb
if { [llength [get_debug_cores -quiet] ] > 0 } {
implement_debug_core
}
place_design
write_checkpoint -force CPU9bits_placed.dcp
create_report "impl_1_place_report_io_0" "report_io -file CPU9bits_io_placed.rpt"
create_report "impl_1_place_report_utilization_0" "report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb"
create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt"
close_msg_db -file place_design.pb
} RESULT]
if {$rc} {
step_failed place_design
return -code error $RESULT
} else {
end_step place_design
unset ACTIVE_STEP
}
start_step route_design
set ACTIVE_STEP route_design
set rc [catch {
create_msg_db route_design.pb
route_design
write_checkpoint -force CPU9bits_routed.dcp
create_report "impl_1_route_report_drc_0" "report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx"
create_report "impl_1_route_report_methodology_0" "report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx"
create_report "impl_1_route_report_power_0" "report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx"
create_report "impl_1_route_report_route_status_0" "report_route_status -file CPU9bits_route_status.rpt -pb CPU9bits_route_status.pb"
create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation "
create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file CPU9bits_incremental_reuse_routed.rpt"
create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file CPU9bits_clock_utilization_routed.rpt"
create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx"
close_msg_db -file route_design.pb
} RESULT]
if {$rc} {
write_checkpoint -force CPU9bits_routed_error.dcp
step_failed route_design
return -code error $RESULT
} else {
end_step route_design
unset ACTIVE_STEP
}

471
lab2CA.runs/impl_1/CPU9bits.vdi
View File

@@ -1,471 +0,0 @@
#-----------------------------------------------------------
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sat Apr 6 17:33:53 2019
# Process ID: 9496
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1
# Command line: vivado.exe -log CPU9bits.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits.vdi
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source CPU9bits.tcl -notrace
Command: link_design -top CPU9bits -part xc7k160tifbg484-2L
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
INFO: [Project 1-570] Preparing netlist for logic optimization
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 577.664 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
6 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:16 . Memory (MB): peak = 583.055 ; gain = 324.613
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.719 . Memory (MB): peak = 595.676 ; gain = 12.621
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 178a9fcd1
Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1128.926 ; gain = 533.250
Starting Logic Optimization Task
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 11e80142d
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.086 . Memory (MB): peak = 1224.855 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 1 cells and removed 1 cells
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 11e80142d
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.090 . Memory (MB): peak = 1224.855 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 3 Sweep
Phase 3 Sweep | Checksum: 11e80142d
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.098 . Memory (MB): peak = 1224.855 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 11e80142d
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.103 . Memory (MB): peak = 1224.855 ; gain = 0.000
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: 8b9eda27
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.145 . Memory (MB): peak = 1224.855 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 8b9eda27
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.147 . Memory (MB): peak = 1224.855 ; gain = 0.000
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 1 | 1 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 0 | 0 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Starting Connectivity Check Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1224.855 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 8b9eda27
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.150 . Memory (MB): peak = 1224.855 ; gain = 0.000
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.000 | TNS=0.000 |
WARNING: [Power 33-232] No user defined clocks were found in the design!
Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 1 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 0 newly gated: 0 Total Ports: 2
Ending PowerOpt Patch Enables Task | Checksum: 8b9eda27
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1334.406 ; gain = 0.000
Ending Power Optimization Task | Checksum: 8b9eda27
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.786 . Memory (MB): peak = 1334.406 ; gain = 109.551
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 8b9eda27
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1334.406 ; gain = 0.000
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1334.406 ; gain = 0.000
Ending Netlist Obfuscation Task | Checksum: 8b9eda27
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1334.406 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
28 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1334.406 ; gain = 751.352
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1334.406 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx
Command: report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.3/data/ip'.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_drc_opted.rpt.
report_drc completed successfully
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 44f3ef01
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1334.406 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: b481c8c5
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 16bafe571
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 16bafe571
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 1 Placer Initialization | Checksum: 16bafe571
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 16bafe571
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1334.406 ; gain = 0.000
WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
Phase 2 Global Placement | Checksum: 187ab5e99
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 187ab5e99
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 168760e64
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 105becb87
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 105becb87
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: cd32f4e6
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: cd32f4e6
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: cd32f4e6
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 3 Detail Placement | Checksum: cd32f4e6
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
Phase 4.1 Post Commit Optimization | Checksum: cd32f4e6
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: cd32f4e6
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: cd32f4e6
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 4.4 Final Placement Cleanup | Checksum: 18c80bbbe
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 18c80bbbe
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000
Ending Placer Task | Checksum: 101790dce
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
45 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1334.406 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.097 . Memory (MB): peak = 1334.406 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file CPU9bits_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1334.406 ; gain = 0.000
INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1334.406 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: 2e37d8f5 ConstDB: 0 ShapeSum: d34134d9 RouteDB: 0
Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 7ebb6ebf
Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 1485.609 ; gain = 151.203
Post Restoration Checksum: NetGraph: 10180109 NumContArr: 6ea36db6 Constraints: 0 Timing: 0
Phase 2 Router Initialization
INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 7ebb6ebf
Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 1489.359 ; gain = 154.953
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 7ebb6ebf
Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 1489.359 ; gain = 154.953
Number of Nodes with overlaps = 0
Phase 2 Router Initialization | Checksum: dbaddab7
Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676
Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: ad0f318a
Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 4
Number of Nodes with overlaps = 0
Phase 4.1 Global Iteration 0 | Checksum: 1246629fb
Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676
Phase 4 Rip-up And Reroute | Checksum: 1246629fb
Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676
Phase 5 Delay and Skew Optimization
Phase 5 Delay and Skew Optimization | Checksum: 1246629fb
Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1 Hold Fix Iter | Checksum: 1246629fb
Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676
Phase 6 Post Hold Fix | Checksum: 1246629fb
Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.00477869 %
Global Horizontal Routing Utilization = 0.00797101 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Congestion Report
North Dir 1x1 Area, Max Cong = 9.00901%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 13.5135%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 16.1765%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 14.7059%, No Congested Regions.
------------------------------
Reporting congestion hotspots
------------------------------
Direction: North
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: South
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: East
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: West
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Phase 7 Route finalize | Checksum: 1246629fb
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 1246629fb
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 1219f5402
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676
INFO: [Route 35-16] Router Completed Successfully
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
57 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:30 . Memory (MB): peak = 1516.082 ; gain = 181.676
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1516.082 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.062 . Memory (MB): peak = 1516.082 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx
Command: report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx
Command: report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx
Command: report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx
WARNING: [Power 33-232] No user defined clocks were found in the design!
Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
68 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file CPU9bits_route_status.rpt -pb CPU9bits_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
INFO: [runtcl-4] Executing : report_incremental_reuse -file CPU9bits_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file CPU9bits_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Common 17-206] Exiting Vivado at Sat Apr 6 17:35:04 2019...

15
lab2CA.runs/impl_1/CPU9bits_bus_skew_routed.rpt
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@@ -1,15 +0,0 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Apr 6 17:35:04 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx
| Design : CPU9bits
| Device : 7k160ti-fbg484
| Speed File : -2L PRODUCTION 1.12 2017-02-17
---------------------------------------------------------------------------------------------------------------------------------------------------------
Bus Skew Report
No bus skew constraints

154
lab2CA.runs/impl_1/CPU9bits_clock_utilization_routed.rpt
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@@ -1,154 +0,0 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Apr 6 17:35:04 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_clock_utilization -file CPU9bits_clock_utilization_routed.rpt
| Design : CPU9bits
| Device : 7k160ti-fbg484
| Speed File : -2L PRODUCTION 1.12 2017-02-17
| Temperature Grade : I
-------------------------------------------------------------------------------------------
Clock Utilization Report
Table of Contents
-----------------
1. Clock Primitive Utilization
2. Global Clock Resources
3. Global Clock Source Details
4. Clock Regions: Key Resource Utilization
5. Clock Regions : Global Clock Summary
6. Device Cell Placement Summary for Global Clock g0
7. Clock Region Cell Placement per Global Clock: Region X0Y1
1. Clock Primitive Utilization
------------------------------
+----------+------+-----------+-----+--------------+--------+
| Type | Used | Available | LOC | Clock Region | Pblock |
+----------+------+-----------+-----+--------------+--------+
| BUFGCTRL | 1 | 32 | 0 | 0 | 0 |
| BUFH | 0 | 120 | 0 | 0 | 0 |
| BUFIO | 0 | 32 | 0 | 0 | 0 |
| BUFMR | 0 | 16 | 0 | 0 | 0 |
| BUFR | 0 | 32 | 0 | 0 | 0 |
| MMCM | 0 | 8 | 0 | 0 | 0 |
| PLL | 0 | 8 | 0 | 0 | 0 |
+----------+------+-----------+-----+--------------+--------+
2. Global Clock Resources
-------------------------
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+
| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+
| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 59 | 0 | | | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG |
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
3. Global Clock Source Details
------------------------------
+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
| src0 | g0 | IBUF/O | None | IOB_X0Y78 | X0Y1 | 1 | 0 | | | clk_IBUF_inst/O | clk_IBUF |
+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
4. Clock Regions: Key Resource Utilization
------------------------------------------
+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 |
| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 58 | 2800 | 29 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 |
| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2200 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
| X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 |
| X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2200 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
| X1Y3 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 2150 | 0 | 800 | 0 | 50 | 0 | 25 | 0 | 60 |
| X0Y4 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
| X1Y4 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2300 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
* Global Clock column represents track count; while other columns represents cell counts
5. Clock Regions : Global Clock Summary
---------------------------------------
All Modules
+----+----+----+
| | X0 | X1 |
+----+----+----+
| Y4 | 0 | 0 |
| Y3 | 0 | 0 |
| Y2 | 0 | 0 |
| Y1 | 1 | 0 |
| Y0 | 0 | 0 |
+----+----+----+
6. Device Cell Placement Summary for Global Clock g0
----------------------------------------------------
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
| g0 | BUFG/O | n/a | | | | 59 | 0 | 0 | 0 | clk_IBUF_BUFG |
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types
+----+-----+----+
| | X0 | X1 |
+----+-----+----+
| Y4 | 0 | 0 |
| Y3 | 0 | 0 |
| Y2 | 0 | 0 |
| Y1 | 59 | 0 |
| Y0 | 0 | 0 |
+----+-----+----+
7. Clock Region Cell Placement per Global Clock: Region X0Y1
------------------------------------------------------------
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+
| g0 | n/a | BUFG/O | None | 59 | 0 | 58 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG |
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
# Location of BUFG Primitives
set_property LOC BUFGCTRL_X0Y0 [get_cells clk_IBUF_BUFG_inst]
# Location of IO Primitives which is load of clock spine
# Location of clock ports
set_property LOC IOB_X0Y78 [get_ports clk]
# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0"
#startgroup
create_pblock {CLKAG_clk_IBUF_BUFG}
add_cells_to_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]]
resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1}
#endgroup

68
lab2CA.runs/impl_1/CPU9bits_control_sets_placed.rpt
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@@ -1,68 +0,0 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Apr 6 17:34:31 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt
| Design : CPU9bits
| Device : xc7k160ti
-------------------------------------------------------------------------------------
Control Set Information
Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information
1. Summary
----------
+----------------------------------------------------------+-------+
| Status | Count |
+----------------------------------------------------------+-------+
| Number of unique control sets | 3 |
| Unused register locations in slices containing registers | 14 |
+----------------------------------------------------------+-------+
2. Histogram
------------
+--------+--------------+
| Fanout | Control Sets |
+--------+--------------+
| 9 | 2 |
| 16+ | 1 |
+--------+--------------+
3. Flip-Flop Distribution
-------------------------
+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No | No | No | 0 | 0 |
| No | No | Yes | 0 | 0 |
| No | Yes | No | 40 | 11 |
| Yes | No | No | 0 | 0 |
| Yes | No | Yes | 0 | 0 |
| Yes | Yes | No | 18 | 6 |
+--------------+-----------------------+------------------------+-----------------+--------------+
4. Detailed Control Set Information
-----------------------------------
+----------------+------------------------+------------------+------------------+----------------+
| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count |
+----------------+------------------------+------------------+------------------+----------------+
| clk_IBUF_BUFG | pipe2/E[0] | reset_IBUF | 3 | 9 |
| clk_IBUF_BUFG | pipe2/Dout_reg[5]_0[0] | reset_IBUF | 3 | 9 |
| clk_IBUF_BUFG | | reset_IBUF | 11 | 40 |
+----------------+------------------------+------------------+------------------+----------------+

61
lab2CA.runs/impl_1/CPU9bits_drc_opted.rpt
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@@ -1,61 +0,0 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Apr 6 17:34:27 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx
| Design : CPU9bits
| Device : xc7k160tifbg484-2L
| Speed File : -2L
| Design State : Synthesized
---------------------------------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 3
+----------+------------------+-----------------------------------------------------+------------+
| Rule | Severity | Description | Violations |
+----------+------------------+-----------------------------------------------------+------------+
| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 |
| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 |
| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
+----------+------------------+-----------------------------------------------------+------------+
2. REPORT DETAILS
-----------------
NSTD-1#1 Critical Warning
Unspecified I/O Standard
12 out of 12 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: result[8:0], clk, done, reset.
Related violations: <none>
UCIO-1#1 Critical Warning
Unconstrained Logical Port
12 out of 12 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: result[8:0], clk, done, reset.
Related violations: <none>
CFGBVS-1#1 Warning
Missing CFGBVS and CONFIG_VOLTAGE Design Properties
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
Related violations: <none>

61
lab2CA.runs/impl_1/CPU9bits_drc_routed.rpt
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@@ -1,61 +0,0 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Apr 6 17:35:02 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx
| Design : CPU9bits
| Device : xc7k160tifbg484-2L
| Speed File : -2L
| Design State : Fully Routed
------------------------------------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 3
+----------+------------------+-----------------------------------------------------+------------+
| Rule | Severity | Description | Violations |
+----------+------------------+-----------------------------------------------------+------------+
| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 |
| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 |
| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
+----------+------------------+-----------------------------------------------------+------------+
2. REPORT DETAILS
-----------------
NSTD-1#1 Critical Warning
Unspecified I/O Standard
12 out of 12 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: result[8:0], clk, done, reset.
Related violations: <none>
UCIO-1#1 Critical Warning
Unconstrained Logical Port
12 out of 12 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: result[8:0], clk, done, reset.
Related violations: <none>
CFGBVS-1#1 Warning
Missing CFGBVS and CONFIG_VOLTAGE Design Properties
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
Related violations: <none>

526
lab2CA.runs/impl_1/CPU9bits_io_placed.rpt
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@@ -1,526 +0,0 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Apr 6 17:34:31 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_io -file CPU9bits_io_placed.rpt
| Design : CPU9bits
| Device : xc7k160ti
| Speed File : -2L
| Package : fbg484
| Package Version : FINAL 2012-06-26
| Package Pin Delay Version : VERS. 2.0 2012-06-26
-------------------------------------------------------------------------------------------------
IO Information
Table of Contents
-----------------
1. Summary
2. IO Assignments by Package Pin
1. Summary
----------
+---------------+
| Total User IO |
+---------------+
| 12 |
+---------------+
2. IO Assignments by Package Pin
--------------------------------
+------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
+------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
| A1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
| A3 | | | MGTXTXN3_115 | Gigabit | | | | | | | | | | | | | | | |
| A4 | | | MGTXTXP3_115 | Gigabit | | | | | | | | | | | | | | | |
| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
| A7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A8 | | High Range | IO_L21N_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
| A9 | | High Range | IO_L21P_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
| A10 | | High Range | IO_L23N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| A11 | | High Range | IO_L23P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A13 | | High Range | IO_L4P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | |
| A14 | | High Range | IO_L4N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | |
| A15 | | High Range | IO_L9N_T1_DQS_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | |
| A16 | | High Range | IO_L8N_T1_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | |
| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| A18 | | High Range | IO_L10N_T1_AD4N_15 | User IO | | 15 | | | | | | | | | | | | | |
| A19 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | |
| A20 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | |
| A21 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | |
| A22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AA1 | | High Performance | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| AA2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AA3 | | High Performance | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| AA4 | | High Performance | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| AA5 | | High Performance | IO_L1P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA6 | | High Performance | IO_L3P_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA7 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
| AA8 | | High Performance | IO_L5N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA9 | | High Performance | IO_L5P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA10 | | High Performance | IO_L4P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA11 | | High Performance | IO_L20P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AA13 | | High Performance | IO_L21N_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA14 | | High Range | IO_L18P_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
| AA15 | | High Range | IO_L18N_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
| AA16 | | High Range | IO_L17P_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
| AA17 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | |
| AA18 | | High Range | IO_L15P_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
| AA19 | | High Range | IO_L10P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
| AA20 | | High Range | IO_L8P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
| AA21 | | High Range | IO_L9P_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
| AA22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB1 | | High Performance | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| AB2 | | High Performance | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| AB3 | | High Performance | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| AB4 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
| AB5 | | High Performance | IO_L1N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB6 | | High Performance | IO_L3N_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB7 | | High Performance | IO_L2N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB8 | | High Performance | IO_L2P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB10 | | High Performance | IO_L4N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB11 | | High Performance | IO_L20N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB12 | | High Performance | IO_L22N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB13 | | High Performance | IO_L22P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB14 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | |
| AB15 | | High Range | IO_L16P_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
| AB16 | | High Range | IO_L16N_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
| AB17 | | High Range | IO_L17N_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
| AB18 | | High Range | IO_L15N_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
| AB19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB20 | | High Range | IO_L10N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
| AB21 | | High Range | IO_L8N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
| AB22 | | High Range | IO_L9N_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
| B1 | | | MGTXTXN2_115 | Gigabit | | | | | | | | | | | | | | | |
| B2 | | | MGTXTXP2_115 | Gigabit | | | | | | | | | | | | | | | |
| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B5 | | | MGTXRXN3_115 | Gigabit | | | | | | | | | | | | | | | |
| B6 | | | MGTXRXP3_115 | Gigabit | | | | | | | | | | | | | | | |
| B7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B8 | | High Range | IO_L22N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| B9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B10 | | High Range | IO_L20N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| B11 | | High Range | IO_L20P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| B12 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | |
| B13 | | High Range | IO_L5N_T0_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | |
| B14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| B15 | | High Range | IO_L9P_T1_DQS_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | |
| B16 | | High Range | IO_L8P_T1_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | |
| B17 | | High Range | IO_L10P_T1_AD4P_15 | User IO | | 15 | | | | | | | | | | | | | |
| B18 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | |
| B19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B20 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | |
| B21 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | |
| B22 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | |
| C1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
| C3 | | | MGTXRXN2_115 | Gigabit | | | | | | | | | | | | | | | |
| C4 | | | MGTXRXP2_115 | Gigabit | | | | | | | | | | | | | | | |
| C5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
| C7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C8 | | High Range | IO_L22P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| C9 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
| C10 | | High Range | IO_L7N_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
| C11 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
| C12 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | |
| C13 | | High Range | IO_L5P_T0_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | |
| C14 | | High Range | IO_L7P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | |
| C15 | | High Range | IO_L7N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | |
| C16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C17 | | High Range | IO_L12P_T1_MRCC_AD5P_15 | User IO | | 15 | | | | | | | | | | | | | |
| C18 | | High Range | IO_L12N_T1_MRCC_AD5N_15 | User IO | | 15 | | | | | | | | | | | | | |
| C19 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | |
| C20 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
| C21 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| C22 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
| D1 | | | MGTXTXN1_115 | Gigabit | | | | | | | | | | | | | | | |
| D2 | | | MGTXTXP1_115 | Gigabit | | | | | | | | | | | | | | | |
| D3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D5 | | | MGTREFCLK0N_115 | Gigabit | | | | | | | | | | | | | | | |
| D6 | | | MGTREFCLK0P_115 | Gigabit | | | | | | | | | | | | | | | |
| D7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D8 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
| D9 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| D10 | | High Range | IO_L7P_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
| D11 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| D12 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | |
| D13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D14 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
| D15 | | High Range | IO_L11P_T1_SRCC_AD12P_15 | User IO | | 15 | | | | | | | | | | | | | |
| D16 | | High Range | IO_L11N_T1_SRCC_AD12N_15 | User IO | | 15 | | | | | | | | | | | | | |
| D17 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| D18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| D19 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | |
| D20 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | |
| D21 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
| D22 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
| E1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
| E3 | | | MGTXRXN1_115 | Gigabit | | | | | | | | | | | | | | | |
| E4 | | | MGTXRXP1_115 | Gigabit | | | | | | | | | | | | | | | |
| E5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E8 | | High Range | IO_24_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| E9 | | High Range | IO_L15N_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
| E10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E11 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| E12 | | High Range | IO_L10N_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
| E13 | | High Range | IO_L10P_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
| E14 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
| E15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| E16 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| E17 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| E18 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| E19 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | |
| E20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E21 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | |
| E22 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | |
| F1 | | | MGTXTXN0_115 | Gigabit | | | | | | | | | | | | | | | |
| F2 | | | MGTXTXP0_115 | Gigabit | | | | | | | | | | | | | | | |
| F3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F5 | | | MGTREFCLK1N_115 | Gigabit | | | | | | | | | | | | | | | |
| F6 | | | MGTREFCLK1P_115 | Gigabit | | | | | | | | | | | | | | | |
| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F8 | | High Range | IO_L17N_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
| F9 | | High Range | IO_L15P_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
| F10 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| F11 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| F12 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
| F13 | | High Range | IO_L8N_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
| F14 | | High Range | IO_6_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
| F15 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | |
| F16 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | |
| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F18 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | |
| F19 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | |
| F20 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | |
| F21 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | |
| F22 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
| G1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
| G3 | | | MGTXRXN0_115 | Gigabit | | | | | | | | | | | | | | | |
| G4 | | | MGTXRXP0_115 | Gigabit | | | | | | | | | | | | | | | |
| G5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
| G7 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | |
| G8 | | High Range | IO_L17P_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
| G9 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
| G10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| G11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| G12 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| G13 | | High Range | IO_L8P_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
| G14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G15 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | |
| G16 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | |
| G17 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | |
| G18 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | |
| G19 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
| G20 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | |
| G21 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
| G22 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | |
| H1 | | | MGTAVTTRCAL_115 | Gigabit | | | | | | | | | | | | | | | |
| H2 | | | MGTRREF_115 | Gigabit | | | | | | | | | | | | | | | |
| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H6 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | |
| H7 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | |
| H8 | | High Range | IO_L16N_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
| H9 | | High Range | IO_L16P_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
| H10 | | High Range | IO_18_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H12 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| H13 | | High Range | IO_L9N_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
| H14 | | High Range | IO_L9P_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
| H15 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | |
| H16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| H17 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
| H18 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | |
| H19 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | |
| H20 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| H21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H22 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | |
| J1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J4 | | | MGTVCCAUX | Gigabit Power | | | | | | | | | | | | | | | |
| J5 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | |
| J6 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | |
| J7 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | |
| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| J10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| J14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| J16 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | |
| J17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | |
| J18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J19 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | |
| J20 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| J21 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | |
| J22 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | |
| K1 | | High Performance | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| K2 | | High Performance | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| K3 | | High Performance | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| K4 | | High Performance | IO_0_VRN_34 | User IO | | 34 | | | | | | | | | | | | | |
| K5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K6 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | |
| K7 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | |
| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| K9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| K11 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | |
| K12 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | |
| K13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| K15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K16 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | |
| K17 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
| K18 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| K19 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | |
| K20 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
| K21 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| K22 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | |
| L1 | | High Performance | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L3 | | High Performance | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| L4 | | High Performance | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
| L5 | | High Performance | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| L6 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | |
| L7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | |
| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| L10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L11 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | |
| L12 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | |
| L13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
| L14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| L16 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
| L18 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | |
| L19 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| L20 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| L21 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | |
| L22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M1 | | High Performance | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| M2 | | High Performance | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| M3 | | High Performance | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| M4 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
| M5 | | High Performance | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| M6 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | |
| M7 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | |
| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| M11 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | |
| M12 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | |
| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M16 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | |
| M17 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| M18 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| M19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M20 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | |
| M21 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | |
| M22 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| N1 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
| N2 | | High Performance | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| N3 | | High Performance | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| N4 | | High Performance | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| N5 | | High Performance | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| N6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N7 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | |
| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N11 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
| N12 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
| N13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
| N14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| N16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N17 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | |
| N18 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| N19 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| N20 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | |
| N21 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
| N22 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| P1 | | High Performance | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| P2 | | High Performance | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| P3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P4 | | High Performance | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| P5 | | High Performance | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| P6 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | |
| P7 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | |
| P8 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| P11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| P15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P16 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | |
| P17 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | |
| P18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
| P19 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | |
| P20 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | |
| P21 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | |
| P22 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | |
| R1 | | High Performance | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| R2 | | High Performance | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| R3 | | High Performance | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| R4 | | High Performance | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| R5 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
| R6 | | High Performance | IO_L8N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| R7 | | High Performance | IO_L8P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| R8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| R10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| R12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| R16 | reset | High Range | IO_L20P_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | |
| R17 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
| R18 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | |
| R19 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
| R20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R21 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | |
| R22 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | |
| T1 | | High Performance | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| T2 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
| T3 | | High Performance | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| T4 | | High Performance | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| T5 | | High Performance | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| T6 | | High Performance | IO_0_VRN_33 | User IO | | 33 | | | | | | | | | | | | | |
| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| T8 | | High Performance | IO_L18N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| T9 | | High Performance | IO_L18P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| T10 | | High Performance | IO_L16N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| T11 | | High Performance | IO_L16P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| T12 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
| T13 | | High Performance | IO_L24P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| T14 | | High Performance | IO_25_VRP_33 | User IO | | 33 | | | | | | | | | | | | | |
| T15 | result[2] | High Range | IO_L24P_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| T16 | done | High Range | IO_L20N_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| T18 | | High Range | IO_L3P_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
| T19 | | High Range | IO_0_13 | User IO | | 13 | | | | | | | | | | | | | |
| T20 | | High Range | IO_L6P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| T21 | | High Range | IO_L1P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| T22 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | |
| U1 | | High Performance | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| U2 | | High Performance | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| U3 | | High Performance | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| U4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| U5 | | High Performance | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| U6 | | High Performance | IO_L10N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| U7 | | High Performance | IO_L10P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| U8 | | High Performance | IO_L9P_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| U9 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
| U10 | | High Performance | IO_L14P_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| U11 | | High Performance | IO_L17N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| U12 | | High Performance | IO_L17P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| U13 | | High Performance | IO_L24N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| U14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| U15 | result[1] | High Range | IO_L24N_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| U16 | | High Range | IO_L19P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| U17 | | High Range | IO_L5P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| U18 | | High Range | IO_L3N_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
| U19 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | |
| U20 | | High Range | IO_L6N_T0_VREF_13 | User IO | | 13 | | | | | | | | | | | | | |
| U21 | | High Range | IO_L1N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| U22 | | High Range | IO_L2P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| V1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| V2 | | High Performance | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| V3 | | High Performance | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| V4 | | High Performance | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| V5 | | High Performance | IO_25_VRP_34 | User IO | | 34 | | | | | | | | | | | | | |
| V6 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
| V7 | | High Performance | IO_L11P_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| V8 | | High Performance | IO_L9N_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| V9 | | High Performance | IO_L14N_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| V10 | | High Performance | IO_L15P_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| V11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| V12 | | High Performance | IO_L23N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| V13 | | High Performance | IO_L23P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| V14 | result[0] | High Range | IO_25_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| V15 | result[4] | High Range | IO_L23P_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| V16 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | |
| V17 | | High Range | IO_L19N_T3_VREF_13 | User IO | | 13 | | | | | | | | | | | | | |
| V18 | | High Range | IO_L5N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| V19 | | High Range | IO_L12P_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
| V20 | clk | High Range | IO_L11P_T1_SRCC_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | |
| V21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| V22 | | High Range | IO_L2N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| W1 | | High Performance | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| W2 | | High Performance | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| W3 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
| W4 | | High Performance | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| W5 | | High Performance | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| W6 | | High Performance | IO_L7P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| W7 | | High Performance | IO_L11N_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| W8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| W9 | | High Performance | IO_L13P_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| W10 | | High Performance | IO_L15N_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| W11 | | High Performance | IO_L6P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| W12 | | High Performance | IO_L19P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| W13 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
| W14 | result[6] | High Range | IO_L22P_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| W15 | result[3] | High Range | IO_L23N_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| W16 | result[8] | High Range | IO_L21P_T3_DQS_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| W17 | | High Range | IO_L14P_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
| W18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| W19 | | High Range | IO_L12N_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
| W20 | | High Range | IO_L11N_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
| W21 | | High Range | IO_L4P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| W22 | | High Range | IO_L4N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| Y1 | | High Performance | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| Y2 | | High Performance | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| Y3 | | High Performance | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| Y4 | | High Performance | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
| Y5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| Y6 | | High Performance | IO_L7N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y7 | | High Performance | IO_L12N_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y8 | | High Performance | IO_L12P_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y9 | | High Performance | IO_L13N_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y10 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
| Y11 | | High Performance | IO_L6N_T0_VREF_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y12 | | High Performance | IO_L19N_T3_VREF_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y13 | | High Performance | IO_L21P_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y14 | result[5] | High Range | IO_L22N_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| Y15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| Y16 | result[7] | High Range | IO_L21N_T3_DQS_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| Y17 | | High Range | IO_L14N_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
| Y18 | | High Range | IO_L13P_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
| Y19 | | High Range | IO_L13N_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
| Y20 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | |
| Y21 | | High Range | IO_L7P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
| Y22 | | High Range | IO_L7N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
* Default value
** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.

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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Apr 6 17:35:03 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx
| Design : CPU9bits
| Device : xc7k160tifbg484-2L
| Speed File : -2L
| Design State : Fully Routed
--------------------------------------------------------------------------------------------------------------------------------------------------------------
Report Methodology
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Max violations: <unlimited>
Violations found: 59
+-----------+----------+-----------------------------+------------+
| Rule | Severity | Description | Violations |
+-----------+----------+-----------------------------+------------+
| TIMING-17 | Warning | Non-clocked sequential cell | 59 |
+-----------+----------+-----------------------------+------------+
2. REPORT DETAILS
-----------------
TIMING-17#1 Warning
Non-clocked sequential cell
The clock pin EM/dM/memory_reg/CLKARDCLK is not reached by a timing clock
Related violations: <none>
TIMING-17#2 Warning
Non-clocked sequential cell
The clock pin FD/FetchU/PC/Dout_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#3 Warning
Non-clocked sequential cell
The clock pin FD/FetchU/PC/Dout_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#4 Warning
Non-clocked sequential cell
The clock pin FD/FetchU/PC/Dout_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#5 Warning
Non-clocked sequential cell
The clock pin FD/RF/r0/Dout_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#6 Warning
Non-clocked sequential cell
The clock pin FD/RF/r0/Dout_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#7 Warning
Non-clocked sequential cell
The clock pin FD/RF/r0/Dout_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#8 Warning
Non-clocked sequential cell
The clock pin FD/RF/r0/Dout_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#9 Warning
Non-clocked sequential cell
The clock pin FD/RF/r0/Dout_reg[4]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#10 Warning
Non-clocked sequential cell
The clock pin FD/RF/r0/Dout_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#11 Warning
Non-clocked sequential cell
The clock pin FD/RF/r0/Dout_reg[6]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#12 Warning
Non-clocked sequential cell
The clock pin FD/RF/r0/Dout_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#13 Warning
Non-clocked sequential cell
The clock pin FD/RF/r0/Dout_reg[8]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#14 Warning
Non-clocked sequential cell
The clock pin FD/RF/r1/Dout_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#15 Warning
Non-clocked sequential cell
The clock pin FD/RF/r1/Dout_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#16 Warning
Non-clocked sequential cell
The clock pin FD/RF/r1/Dout_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#17 Warning
Non-clocked sequential cell
The clock pin FD/RF/r1/Dout_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#18 Warning
Non-clocked sequential cell
The clock pin FD/RF/r1/Dout_reg[4]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#19 Warning
Non-clocked sequential cell
The clock pin FD/RF/r1/Dout_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#20 Warning
Non-clocked sequential cell
The clock pin FD/RF/r1/Dout_reg[6]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#21 Warning
Non-clocked sequential cell
The clock pin FD/RF/r1/Dout_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#22 Warning
Non-clocked sequential cell
The clock pin FD/RF/r1/Dout_reg[8]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#23 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[12]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#24 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[24]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#25 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[25]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#26 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[26]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#27 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[27]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#28 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[28]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#29 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[29]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#30 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#31 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[30]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#32 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[31]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#33 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[32]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#34 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[33]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#35 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[34]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#36 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[35]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#37 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[36]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#38 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[37]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#39 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[38]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#40 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[39]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#41 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[40]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#42 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[41]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#43 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[45]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#44 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#45 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#46 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[25]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#47 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[26]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#48 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[27]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#49 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[28]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#50 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[29]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#51 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[30]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#52 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[31]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#53 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[32]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#54 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[33]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#55 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[34]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#56 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[35]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#57 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[36]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#58 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#59 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[5]/C is not reached by a timing clock
Related violations: <none>

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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Apr 6 17:35:04 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx
| Design : CPU9bits
| Device : xc7k160tifbg484-2L
| Design State : routed
| Grade : industrial
| Process : typical
| Characterization : Production
----------------------------------------------------------------------------------------------------------------------------------------------
Power Report
Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy
1. Summary
----------
+--------------------------+--------------+
| Total On-Chip Power (W) | 10.632 |
| Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA |
| Dynamic (W) | 10.494 |
| Device Static (W) | 0.137 |
| Effective TJA (C/W) | 2.5 |
| Max Ambient (C) | 73.7 |
| Junction Temperature (C) | 51.3 |
| Confidence Level | Low |
| Setting File | --- |
| Simulation Activity File | --- |
| Design Nets Matched | NA |
+--------------------------+--------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
1.1 On-Chip Components
----------------------
+----------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+----------------+-----------+----------+-----------+-----------------+
| Slice Logic | 0.768 | 132 | --- | --- |
| LUT as Logic | 0.719 | 54 | 101400 | 0.05 |
| Register | 0.043 | 58 | 202800 | 0.03 |
| BUFG | 0.005 | 1 | 32 | 3.13 |
| Others | 0.000 | 5 | --- | --- |
| Signals | 0.881 | 109 | --- | --- |
| Block RAM | 0.060 | 0.5 | 325 | 0.15 |
| I/O | 8.785 | 12 | 285 | 4.21 |
| Static Power | 0.137 | | | |
| Total | 10.632 | | | |
+----------------+-----------+----------+-----------+-----------------+
1.2 Power Supply Summary
------------------------
+-----------+-------------+-----------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+
| Vccint | 0.950 | 1.868 | 1.799 | 0.070 |
| Vccaux | 1.800 | 0.738 | 0.719 | 0.020 |
| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 |
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
| Vcco18 | 1.800 | 4.161 | 4.160 | 0.001 |
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 |
| Vccbram | 0.950 | 0.006 | 0.005 | 0.002 |
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 |
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 |
| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 |
| Vccadc | 1.800 | 0.018 | 0.000 | 0.018 |
+-----------+-------------+-----------+-------------+------------+
1.3 Confidence Level
--------------------
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| User Input Data | Confidence | Details | Action |
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| Design implementation state | High | Design is routed | |
| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view |
| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models | High | Device models are Production | |
| | | | |
| Overall confidence level | Low | | |
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
2. Settings
-----------
2.1 Environment
---------------
+-----------------------+--------------------------+
| Ambient Temp (C) | 25.0 |
| ThetaJA (C/W) | 2.5 |
| Airflow (LFM) | 250 |
| Heat Sink | medium (Medium Profile) |
| ThetaSA (C/W) | 4.2 |
| Board Selection | medium (10"x10") |
| # of Board Layers | 12to15 (12 to 15 Layers) |
| Board Temperature (C) | 25.0 |
+-----------------------+--------------------------+
2.2 Clock Constraints
---------------------
+-------+--------+-----------------+
| Clock | Domain | Constraint (ns) |
+-------+--------+-----------------+
3. Detailed Reports
-------------------
3.1 By Hierarchy
----------------
+------------+-----------+
| Name | Power (W) |
+------------+-----------+
| CPU9bits | 10.494 |
| EM | 0.099 |
| dM | 0.099 |
| FD | 0.424 |
| FetchU | 0.179 |
| PC | 0.179 |
| RF | 0.244 |
| r0 | 0.133 |
| r1 | 0.112 |
| W | 0.301 |
| mux5 | 0.301 |
| pipe1 | 0.782 |
| pipe2 | 0.087 |
+------------+-----------+

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Design Route Status
: # nets :
------------------------------------------- : ----------- :
# of logical nets.......................... : 152 :
# of nets not needing routing.......... : 41 :
# of internally routed nets........ : 41 :
# of routable nets..................... : 111 :
# of fully routed nets............. : 111 :
# of nets with routing errors.......... : 0 :
------------------------------------------- : ----------- :

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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Apr 6 17:35:04 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation
| Design : CPU9bits
| Device : 7k160ti-fbg484
| Speed File : -2L PRODUCTION 1.12 2017-02-17
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Timing Summary Report
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : false
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
check_timing report
Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops
1. checking no_clock
--------------------
There are 59 register/latch pins with no clock driven by root clock pin: clk (HIGH)
2. checking constant_clock
--------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock
-----------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints
--------------------------------------------
There are 152 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay
--------------------------
There is 1 input port with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay
---------------------------
There are 10 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock
--------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks
----------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops
-----------------
There are 0 combinational loops in the design.
10. checking partial_input_delay
--------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay
---------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops
------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
NA NA NA NA NA NA NA NA NA NA NA NA
There are no user specified timing constraints.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------

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lab2CA.runs/impl_1/CPU9bits_utilization_placed.pb
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212
lab2CA.runs/impl_1/CPU9bits_utilization_placed.rpt
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@@ -1,212 +0,0 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Apr 6 17:34:31 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb
| Design : CPU9bits
| Device : 7k160tifbg484-2L
| Design State : Fully Placed
-------------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Slice Logic Distribution
3. Memory
4. DSP
5. IO and GT Specific
6. Clocking
7. Specific Feature
8. Primitives
9. Black Boxes
10. Instantiated Netlists
1. Slice Logic
--------------
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs | 54 | 0 | 101400 | 0.05 |
| LUT as Logic | 54 | 0 | 101400 | 0.05 |
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
| Slice Registers | 58 | 0 | 202800 | 0.03 |
| Register as Flip Flop | 58 | 0 | 202800 | 0.03 |
| Register as Latch | 0 | 0 | 202800 | 0.00 |
| F7 Muxes | 0 | 0 | 50700 | 0.00 |
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
+-------------------------+------+-------+-----------+-------+
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 58 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Slice Logic Distribution
---------------------------
+--------------------------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+--------------------------------------------+------+-------+-----------+-------+
| Slice | 21 | 0 | 25350 | 0.08 |
| SLICEL | 12 | 0 | | |
| SLICEM | 9 | 0 | | |
| LUT as Logic | 54 | 0 | 101400 | 0.05 |
| using O5 output only | 0 | | | |
| using O6 output only | 40 | | | |
| using O5 and O6 | 14 | | | |
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | | |
| LUT as Shift Register | 0 | 0 | | |
| Slice Registers | 58 | 0 | 202800 | 0.03 |
| Register driven from within the Slice | 34 | | | |
| Register driven from outside the Slice | 24 | | | |
| LUT in front of the register is unused | 17 | | | |
| LUT in front of the register is used | 7 | | | |
| Unique Control Sets | 3 | | 25350 | 0.01 |
+--------------------------------------------+------+-------+-----------+-------+
* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets.
3. Memory
---------
+-------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile | 0.5 | 0 | 325 | 0.15 |
| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 |
| RAMB18 | 1 | 0 | 650 | 0.15 |
| RAMB18E1 only | 1 | | | |
+-------------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
4. DSP
------
+-----------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+-------+
| DSPs | 0 | 0 | 600 | 0.00 |
+-----------+------+-------+-----------+-------+
5. IO and GT Specific
---------------------
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 12 | 0 | 285 | 4.21 |
| IOB Master Pads | 6 | | | |
| IOB Slave Pads | 5 | | | |
| Bonded IPADs | 0 | 0 | 14 | 0.00 |
| Bonded OPADs | 0 | 0 | 8 | 0.00 |
| PHY_CONTROL | 0 | 0 | 8 | 0.00 |
| PHASER_REF | 0 | 0 | 8 | 0.00 |
| OUT_FIFO | 0 | 0 | 32 | 0.00 |
| IN_FIFO | 0 | 0 | 32 | 0.00 |
| IDELAYCTRL | 0 | 0 | 8 | 0.00 |
| IBUFDS | 0 | 0 | 275 | 0.00 |
| GTXE2_COMMON | 0 | 0 | 1 | 0.00 |
| GTXE2_CHANNEL | 0 | 0 | 4 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 |
| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 |
| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 |
| ILOGIC | 0 | 0 | 285 | 0.00 |
| OLOGIC | 0 | 0 | 285 | 0.00 |
+-----------------------------+------+-------+-----------+-------+
6. Clocking
-----------
+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL | 1 | 0 | 32 | 3.13 |
| BUFIO | 0 | 0 | 32 | 0.00 |
| MMCME2_ADV | 0 | 0 | 8 | 0.00 |
| PLLE2_ADV | 0 | 0 | 8 | 0.00 |
| BUFMRCE | 0 | 0 | 16 | 0.00 |
| BUFHCE | 0 | 0 | 120 | 0.00 |
| BUFR | 0 | 0 | 32 | 0.00 |
+------------+------+-------+-----------+-------+
7. Specific Feature
-------------------
+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+
8. Primitives
-------------
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDRE | 58 | Flop & Latch |
| LUT4 | 23 | LUT |
| LUT3 | 18 | LUT |
| LUT5 | 11 | LUT |
| OBUF | 10 | IO |
| LUT6 | 9 | LUT |
| LUT2 | 6 | LUT |
| IBUF | 2 | IO |
| RAMB18E1 | 1 | Block Memory |
| LUT1 | 1 | LUT |
| BUFG | 1 | Clock |
+----------+------+---------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+

196
lab2CA.runs/impl_1/gen_run.xml
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@@ -1,196 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="impl_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1554586396">
<File Type="BITSTR-BMM" Name="CPU9bits_bd.bmm"/>
<File Type="OPT-METHODOLOGY-DRC" Name="CPU9bits_methodology_drc_opted.rpt"/>
<File Type="INIT-TIMING" Name="CPU9bits_timing_summary_init.rpt"/>
<File Type="ROUTE-PWR" Name="CPU9bits_power_routed.rpt"/>
<File Type="PA-TCL" Name="CPU9bits.tcl"/>
<File Type="OPT-TIMING" Name="CPU9bits_timing_summary_opted.rpt"/>
<File Type="OPT-DCP" Name="CPU9bits_opt.dcp"/>
<File Type="ROUTE-PWR-SUM" Name="CPU9bits_power_summary_routed.pb"/>
<File Type="REPORTS-TCL" Name="CPU9bits_reports.tcl"/>
<File Type="OPT-DRC" Name="CPU9bits_drc_opted.rpt"/>
<File Type="OPT-HWDEF" Name="CPU9bits.hwdef"/>
<File Type="PWROPT-DCP" Name="CPU9bits_pwropt.dcp"/>
<File Type="PWROPT-DRC" Name="CPU9bits_drc_pwropted.rpt"/>
<File Type="PWROPT-TIMING" Name="CPU9bits_timing_summary_pwropted.rpt"/>
<File Type="PLACE-DCP" Name="CPU9bits_placed.dcp"/>
<File Type="PLACE-IO" Name="CPU9bits_io_placed.rpt"/>
<File Type="PLACE-CLK" Name="CPU9bits_clock_utilization_placed.rpt"/>
<File Type="PLACE-UTIL" Name="CPU9bits_utilization_placed.rpt"/>
<File Type="PLACE-UTIL-PB" Name="CPU9bits_utilization_placed.pb"/>
<File Type="PLACE-CTRL" Name="CPU9bits_control_sets_placed.rpt"/>
<File Type="PLACE-SIMILARITY" Name="CPU9bits_incremental_reuse_placed.rpt"/>
<File Type="PLACE-PRE-SIMILARITY" Name="CPU9bits_incremental_reuse_pre_placed.rpt"/>
<File Type="BG-BGN" Name="CPU9bits.bgn"/>
<File Type="PLACE-TIMING" Name="CPU9bits_timing_summary_placed.rpt"/>
<File Type="POSTPLACE-PWROPT-DCP" Name="CPU9bits_postplace_pwropt.dcp"/>
<File Type="BG-BIN" Name="CPU9bits.bin"/>
<File Type="POSTPLACE-PWROPT-TIMING" Name="CPU9bits_timing_summary_postplace_pwropted.rpt"/>
<File Type="PHYSOPT-DCP" Name="CPU9bits_physopt.dcp"/>
<File Type="PHYSOPT-DRC" Name="CPU9bits_drc_physopted.rpt"/>
<File Type="BITSTR-MSK" Name="CPU9bits.msk"/>
<File Type="PHYSOPT-TIMING" Name="CPU9bits_timing_summary_physopted.rpt"/>
<File Type="ROUTE-ERROR-DCP" Name="CPU9bits_routed_error.dcp"/>
<File Type="ROUTE-DCP" Name="CPU9bits_routed.dcp"/>
<File Type="ROUTE-BLACKBOX-DCP" Name="CPU9bits_routed_bb.dcp"/>
<File Type="ROUTE-DRC" Name="CPU9bits_drc_routed.rpt"/>
<File Type="ROUTE-DRC-PB" Name="CPU9bits_drc_routed.pb"/>
<File Type="BITSTR-LTX" Name="debug_nets.ltx"/>
<File Type="BITSTR-LTX" Name="CPU9bits.ltx"/>
<File Type="ROUTE-DRC-RPX" Name="CPU9bits_drc_routed.rpx"/>
<File Type="BITSTR-MMI" Name="CPU9bits.mmi"/>
<File Type="ROUTE-METHODOLOGY-DRC" Name="CPU9bits_methodology_drc_routed.rpt"/>
<File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="CPU9bits_methodology_drc_routed.rpx"/>
<File Type="BITSTR-SYSDEF" Name="CPU9bits.sysdef"/>
<File Type="ROUTE-METHODOLOGY-DRC-PB" Name="CPU9bits_methodology_drc_routed.pb"/>
<File Type="ROUTE-PWR-RPX" Name="CPU9bits_power_routed.rpx"/>
<File Type="ROUTE-STATUS" Name="CPU9bits_route_status.rpt"/>
<File Type="ROUTE-STATUS-PB" Name="CPU9bits_route_status.pb"/>
<File Type="ROUTE-TIMINGSUMMARY" Name="CPU9bits_timing_summary_routed.rpt"/>
<File Type="ROUTE-TIMING-PB" Name="CPU9bits_timing_summary_routed.pb"/>
<File Type="ROUTE-TIMING-RPX" Name="CPU9bits_timing_summary_routed.rpx"/>
<File Type="ROUTE-SIMILARITY" Name="CPU9bits_incremental_reuse_routed.rpt"/>
<File Type="ROUTE-CLK" Name="CPU9bits_clock_utilization_routed.rpt"/>
<File Type="ROUTE-BUS-SKEW" Name="CPU9bits_bus_skew_routed.rpt"/>
<File Type="ROUTE-BUS-SKEW-PB" Name="CPU9bits_bus_skew_routed.pb"/>
<File Type="ROUTE-BUS-SKEW-RPX" Name="CPU9bits_bus_skew_routed.rpx"/>
<File Type="POSTROUTE-PHYSOPT-DCP" Name="CPU9bits_postroute_physopt.dcp"/>
<File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="CPU9bits_postroute_physopt_bb.dcp"/>
<File Type="POSTROUTE-PHYSOPT-TIMING" Name="CPU9bits_timing_summary_postroute_physopted.rpt"/>
<File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="CPU9bits_timing_summary_postroute_physopted.pb"/>
<File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="CPU9bits_timing_summary_postroute_physopted.rpx"/>
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW" Name="CPU9bits_bus_skew_postroute_physopted.rpt"/>
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW-PB" Name="CPU9bits_bus_skew_postroute_physopted.pb"/>
<File Type="BG-BIT" Name="CPU9bits.bit"/>
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW-RPX" Name="CPU9bits_bus_skew_postroute_physopted.rpx"/>
<File Type="BITSTR-RBT" Name="CPU9bits.rbt"/>
<File Type="BITSTR-NKY" Name="CPU9bits.nky"/>
<File Type="BG-DRC" Name="CPU9bits.drc"/>
<File Type="RDI-RDI" Name="CPU9bits.vdi"/>
<File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/ALU.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/BasicModules.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/ControlUnit.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/EMModule.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/FDModule.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/FetchUnit.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/RegFile.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/WMUdule.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/dataMemory.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/instructionMemory.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/CPU9bits.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/bd/design_1/design_1.bd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../Downloads/pipeline_example.v">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="CPU9bits"/>
</Config>
</FileSet>
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
</GenRun>

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lab2CA.runs/impl_1/place_design.pb
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12
lab2CA.runs/impl_1/vivado.jou
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@@ -1,12 +0,0 @@
#-----------------------------------------------------------
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sat Apr 6 17:33:53 2019
# Process ID: 9496
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1
# Command line: vivado.exe -log CPU9bits.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits.vdi
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source CPU9bits.tcl -notrace

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BIN
lab2CA.runs/synth_1/CPU9bits.dcp
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32
lab2CA.runs/synth_1/CPU9bits_tb.tcl → lab2CA.runs/synth_1/CPU9bits.tcl
View File

@@ -17,32 +17,30 @@ proc create_report { reportName command } {
send_msg_id runtcl-5 warning "$msg"
}
}
set_param synth.incrementalSynthesisCache C:/Users/ecelab/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-10176-DESKTOP-8QFGS52/incrSyn
set_msg_config -id {Synth 8-256} -limit 10000
set_msg_config -id {Synth 8-638} -limit 10000
set_msg_config -id {Vivado 12-818} -string {{WARNING: [Vivado 12-818] No files matched 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/Bank_behav1.wcfg'}} -suppress
create_project -in_memory -part xc7k160tifbg484-2L
set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_property webtalk.parent_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.cache/wt [current_project]
set_property parent.project_path C:/Users/ecelab/ECE3570-Lab/lab2CA.xpr [current_project]
set_property webtalk.parent_dir {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.cache/wt} [current_project]
set_property parent.project_path {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.xpr} [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language Verilog [current_project]
set_property ip_output_repo c:/Users/ecelab/ECE3570-Lab/lab2CA.cache/ip [current_project]
set_property ip_output_repo {c:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.cache/ip} [current_project]
set_property ip_cache_permissions {read write} [current_project]
read_verilog -library xil_defaultlib {
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/EMModule.v
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FDModule.v
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/WMUdule.v
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v}
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v}
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v}
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/EMModule.v}
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FDModule.v}
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v}
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v}
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/WMUdule.v}
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v}
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v}
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v}
}
# Mark all dcp files as not used in implementation to prevent them from being
# stitched into the results of this synthesis run. Any black boxes in the

309
lab2CA.runs/synth_1/CPU9bits_tb.vds → lab2CA.runs/synth_1/CPU9bits.vds
View File

@@ -2,12 +2,12 @@
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sat Apr 6 17:33:19 2019
# Process ID: 7092
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1
# Start of session at: Wed Apr 10 12:49:25 2019
# Process ID: 13540
# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1
# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou
# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds
# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou
#-----------------------------------------------------------
source CPU9bits.tcl -notrace
Command: synth_design -top CPU9bits -part xc7k160tifbg484-2L
@@ -15,106 +15,102 @@ Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 7732
INFO: Helper process launched with PID 17664
---------------------------------------------------------------------------------
Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 359.789 ; gain = 101.883
Starting Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 362.465 ; gain = 101.664
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
INFO: [Synth 8-6157] synthesizing module 'FDModule' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FDModule.v:3]
INFO: [Synth 8-6157] synthesizing module 'instructionMemory' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
INFO: [Synth 8-6155] done synthesizing module 'instructionMemory' (1#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
INFO: [Synth 8-6157] synthesizing module 'register' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:773]
INFO: [Synth 8-6155] done synthesizing module 'register' (2#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:773]
INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (3#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (4#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:332]
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:338]
INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (5#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:332]
INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (6#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:268]
WARNING: [Synth 8-567] referenced signal 'En' should be on the sensitivity list [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:266]
INFO: [Synth 8-6155] done synthesizing module 'decoder' (7#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:403]
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:408]
INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (8#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:403]
INFO: [Synth 8-6155] done synthesizing module 'RegFile' (9#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:13]
INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (10#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
INFO: [Synth 8-6155] done synthesizing module 'FDModule' (11#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FDModule.v:3]
INFO: [Synth 8-6157] synthesizing module 'fDPipReg' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:849]
INFO: [Synth 8-6155] done synthesizing module 'fDPipReg' (12#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:849]
INFO: [Synth 8-6157] synthesizing module 'EMModule' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/EMModule.v:5]
INFO: [Synth 8-6157] synthesizing module 'dataMemory' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
INFO: [Synth 8-6155] done synthesizing module 'dataMemory' (13#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1341]
INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1406]
INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:683]
INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (14#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:683]
INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (15#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1406]
INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (16#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1341]
INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:720]
INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (17#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:720]
INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:639]
INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (18#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:639]
INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (19#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:883]
INFO: [Synth 8-6155] done synthesizing module 'shift_left' (20#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:883]
INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:957]
INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (21#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:957]
INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:920]
INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (22#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:920]
INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:316]
INFO: [Synth 8-6155] done synthesizing module 'less_than' (23#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:316]
INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1455]
INFO: [Synth 8-6155] done synthesizing module 'BEQ' (24#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1455]
INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:531]
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:537]
INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (25#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:531]
INFO: [Synth 8-6155] done synthesizing module 'ALU' (26#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
INFO: [Synth 8-6157] synthesizing module 'sign_extend_3bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1026]
INFO: [Synth 8-6155] done synthesizing module 'sign_extend_3bit' (27#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1026]
INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:346]
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:352]
INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (28#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:346]
INFO: [Synth 8-6155] done synthesizing module 'EMModule' (29#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/EMModule.v:5]
INFO: [Synth 8-6157] synthesizing module 'eMPipReg' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:866]
INFO: [Synth 8-6155] done synthesizing module 'eMPipReg' (30#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:866]
WARNING: [Synth 8-689] width (62) of port connection 'Din' does not match port width (61) of module 'eMPipReg' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:49]
WARNING: [Synth 8-689] width (62) of port connection 'Dout' does not match port width (61) of module 'eMPipReg' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:50]
INFO: [Synth 8-6157] synthesizing module 'WMUdule' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/WMUdule.v:3]
INFO: [Synth 8-6155] done synthesizing module 'WMUdule' (31#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/WMUdule.v:3]
INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (32#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
WARNING: [Synth 8-3331] design WMUdule has unconnected port reset
WARNING: [Synth 8-3331] design WMUdule has unconnected port clk
INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
INFO: [Synth 8-6157] synthesizing module 'FDModule' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FDModule.v:3]
INFO: [Synth 8-6157] synthesizing module 'instructionMemory' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
INFO: [Synth 8-6155] done synthesizing module 'instructionMemory' (1#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
INFO: [Synth 8-6157] synthesizing module 'register' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:773]
INFO: [Synth 8-6155] done synthesizing module 'register' (2#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:773]
INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (3#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (4#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:332]
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:338]
INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (5#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:332]
INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (6#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:268]
INFO: [Synth 8-6155] done synthesizing module 'decoder' (7#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:403]
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:408]
INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (8#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:403]
INFO: [Synth 8-6155] done synthesizing module 'RegFile' (9#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:14]
INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (10#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
INFO: [Synth 8-6155] done synthesizing module 'FDModule' (11#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FDModule.v:3]
INFO: [Synth 8-6157] synthesizing module 'fDPipReg' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:849]
INFO: [Synth 8-6155] done synthesizing module 'fDPipReg' (12#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:849]
INFO: [Synth 8-6157] synthesizing module 'EMModule' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/EMModule.v:5]
INFO: [Synth 8-6157] synthesizing module 'dataMemory' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
INFO: [Synth 8-6155] done synthesizing module 'dataMemory' (13#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1341]
INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1406]
INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:683]
INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (14#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:683]
INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (15#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1406]
INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (16#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1341]
INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:720]
INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (17#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:720]
INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:639]
INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (18#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:639]
INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (19#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:883]
INFO: [Synth 8-6155] done synthesizing module 'shift_left' (20#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:883]
INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:957]
INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (21#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:957]
INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:920]
INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (22#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:920]
INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:316]
INFO: [Synth 8-6155] done synthesizing module 'less_than' (23#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:316]
INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1455]
INFO: [Synth 8-6155] done synthesizing module 'BEQ' (24#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1455]
INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:531]
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:537]
INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (25#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:531]
INFO: [Synth 8-6155] done synthesizing module 'ALU' (26#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
INFO: [Synth 8-6157] synthesizing module 'sign_extend_3bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1026]
INFO: [Synth 8-6155] done synthesizing module 'sign_extend_3bit' (27#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1026]
INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:346]
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:352]
INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (28#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:346]
INFO: [Synth 8-6155] done synthesizing module 'EMModule' (29#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/EMModule.v:5]
INFO: [Synth 8-6157] synthesizing module 'eMPipReg' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:866]
INFO: [Synth 8-6155] done synthesizing module 'eMPipReg' (30#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:866]
INFO: [Synth 8-6157] synthesizing module 'WMUdule' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/WMUdule.v:3]
INFO: [Synth 8-6155] done synthesizing module 'WMUdule' (31#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/WMUdule.v:3]
INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (32#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
WARNING: [Synth 8-3331] design dataMemory has unconnected port address[8]
WARNING: [Synth 8-3331] design dataMemory has unconnected port address[7]
WARNING: [Synth 8-3331] design EMModule has unconnected port PipIn[50]
WARNING: [Synth 8-3331] design EMModule has unconnected port PipIn[49]
WARNING: [Synth 8-3331] design EMModule has unconnected port PipIn[48]
WARNING: [Synth 8-3331] design EMModule has unconnected port PipIn[47]
---------------------------------------------------------------------------------
Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 416.430 ; gain = 158.523
Finished Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 418.434 ; gain = 157.633
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 416.430 ; gain = 158.523
Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 418.434 ; gain = 157.633
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7k160tifbg484-2L
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 416.430 ; gain = 158.523
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 418.434 ; gain = 157.633
---------------------------------------------------------------------------------
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
INFO: [Synth 8-5544] ROM "memory" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 416.430 ; gain = 158.523
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 418.434 ; gain = 157.633
---------------------------------------------------------------------------------
INFO: [Synth 8-223] decloning instance 'EM/SE1' (sign_extend_3bit) to 'EM/SE3'
@@ -131,13 +127,12 @@ Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 162
+---Registers :
61 Bit Registers := 1
62 Bit Registers := 1
51 Bit Registers := 1
9 Bit Registers := 10
+---RAMs :
4K Bit RAMs := 1
909 Bit RAMs := 1
+---Muxes :
7 Input 9 Bit Muxes := 1
2 Input 9 Bit Muxes := 8
4 Input 9 Bit Muxes := 4
2 Input 4 Bit Muxes := 2
@@ -155,10 +150,6 @@ Finished RTL Component Statistics
Start RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
Hierarchical RTL Component report
Module instructionMemory
Detailed RTL Component Info :
+---Muxes :
7 Input 9 Bit Muxes := 1
Module register
Detailed RTL Component Info :
+---Registers :
@@ -197,7 +188,7 @@ Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 1
+---RAMs :
4K Bit RAMs := 1
909 Bit RAMs := 1
Module bit1_mux_2_1
Detailed RTL Component Info :
+---Muxes :
@@ -205,7 +196,7 @@ Detailed RTL Component Info :
Module eMPipReg
Detailed RTL Component Info :
+---Registers :
61 Bit Registers := 1
62 Bit Registers := 1
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
@@ -223,33 +214,27 @@ No constraint files found.
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[46]' (FDRE) to 'pipe1/Dout_reg[44]'
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[50]' (FDRE) to 'pipe1/Dout_reg[17]'
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[48]' (FDRE) to 'pipe1/Dout_reg[17]'
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[42]' (FDRE) to 'pipe1/Dout_reg[44]'
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[44]' (FDRE) to 'pipe1/Dout_reg[0]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\pipe1/Dout_reg[0] )
INFO: [Synth 8-3886] merging instance 'pipe2/Dout_reg[4]' (FDRE) to 'pipe2/Dout_reg[6]'
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[10]' (FDRE) to 'pipe1/Dout_reg[3]'
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[4]' (FDRE) to 'pipe1/Dout_reg[14]'
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[9]' (FDRE) to 'pipe1/Dout_reg[14]'
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[14]' (FDRE) to 'pipe1/Dout_reg[11]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\pipe1/Dout_reg[11] )
INFO: [Synth 8-3886] merging instance 'pipe2/Dout_reg[1]' (FDRE) to 'pipe2/Dout_reg[2]'
INFO: [Synth 8-3886] merging instance 'pipe2/Dout_reg[2]' (FDRE) to 'pipe1/Dout_reg[11]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\pipe1/Dout_reg[11] )
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 585.000 ; gain = 327.094
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 594.785 ; gain = 333.984
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
ROM:
+------------------+------------+---------------+----------------+
|Module Name | RTL Object | Depth x Width | Implemented As |
+------------------+------------+---------------+----------------+
|instructionMemory | p_0_out | 64x9 | LUT |
|CPU9bits | p_0_out | 64x9 | LUT |
+------------------+------------+---------------+----------------+
Block RAM: Preliminary Mapping Report (see note below)
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|dataMemory: | memory_reg | 512 x 9(NO_CHANGE) | W | R | | | | Port A | 1 | 0 |
|dataMemory: | memory_reg | 128 x 9(NO_CHANGE) | W | R | | | | Port A | 1 | 0 |
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.
@@ -267,7 +252,7 @@ No constraint files found.
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 585.000 ; gain = 327.094
Finished Timing Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 594.785 ; gain = 333.984
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
@@ -277,7 +262,7 @@ Block RAM: Final Mapping Report
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|dataMemory: | memory_reg | 512 x 9(NO_CHANGE) | W | R | | | | Port A | 1 | 0 |
|dataMemory: | memory_reg | 128 x 9(NO_CHANGE) | W | R | | | | Port A | 1 | 0 |
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
---------------------------------------------------------------------------------
@@ -292,12 +277,8 @@ Report RTL Partitions:
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[3]' (FDRE) to 'pipe1/Dout_reg[6]'
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[5]' (FDRE) to 'pipe1/Dout_reg[7]'
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[8]' (FDRE) to 'pipe1/Dout_reg[6]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\pipe1/Dout_reg[6] )
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 585.000 ; gain = 327.094
Finished Technology Mapping : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 594.785 ; gain = 333.984
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -321,7 +302,7 @@ Start Final Netlist Cleanup
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 585.000 ; gain = 327.094
Finished IO Insertion : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
---------------------------------------------------------------------------------
Report Check Netlist:
@@ -334,7 +315,7 @@ Report Check Netlist:
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 585.000 ; gain = 327.094
Finished Renaming Generated Instances : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -346,25 +327,25 @@ Report RTL Partitions:
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 585.000 ; gain = 327.094
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 585.000 ; gain = 327.094
Finished Renaming Generated Ports : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 585.000 ; gain = 327.094
Finished Handling Custom Attributes : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 585.000 ; gain = 327.094
Finished Renaming Generated Nets : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
@@ -381,59 +362,67 @@ Report Cell Usage:
| |Cell |Count |
+------+---------+------+
|1 |BUFG | 1|
|2 |LUT1 | 1|
|3 |LUT2 | 6|
|4 |LUT3 | 17|
|5 |LUT4 | 23|
|6 |LUT5 | 11|
|7 |LUT6 | 9|
|2 |LUT1 | 2|
|3 |LUT2 | 9|
|4 |LUT3 | 22|
|5 |LUT4 | 25|
|6 |LUT5 | 42|
|7 |LUT6 | 101|
|8 |MUXF7 | 1|
|9 |RAMB18E1 | 1|
|10 |FDRE | 58|
|10 |FDRE | 181|
|11 |IBUF | 2|
|12 |OBUF | 10|
+------+---------+------+
Report Instance Areas:
+------+-----------+-----------+------+
| |Instance |Module |Cells |
+------+-----------+-----------+------+
|1 |top | | 140|
|2 | EM |EMModule | 1|
|3 | dM |dataMemory | 1|
|4 | FD |FDModule | 46|
|5 | FetchU |FetchUnit | 10|
|6 | PC |register_1 | 10|
|7 | RF |RegFile | 36|
|8 | r0 |register | 18|
|9 | r1 |register_0 | 18|
|10 | W |WMUdule | 9|
|11 | mux5 |mux_2_1 | 9|
|12 | pipe1 |fDPipReg | 55|
|13 | pipe2 |eMPipReg | 16|
+------+-----------+-----------+------+
+------+-----------+------------+------+
| |Instance |Module |Cells |
+------+-----------+------------+------+
|1 |top | | 397|
|2 | EM |EMModule | 46|
|3 | Bank |RegFile_4 | 45|
|4 | r0 |register_5 | 17|
|5 | r1 |register_6 | 10|
|6 | r2 |register_7 | 9|
|7 | r3 |register_8 | 9|
|8 | dM |dataMemory | 1|
|9 | FD |FDModule | 105|
|10 | CU |ControlUnit | 9|
|11 | FetchU |FetchUnit | 42|
|12 | PC |register_3 | 42|
|13 | RF |RegFile | 54|
|14 | r0 |register | 9|
|15 | r1 |register_0 | 27|
|16 | r2 |register_1 | 9|
|17 | r3 |register_2 | 9|
|18 | W |WMUdule | 18|
|19 | mux5 |mux_2_1 | 18|
|20 | pipe1 |fDPipReg | 154|
|21 | pipe2 |eMPipReg | 61|
+------+-----------+------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 585.000 ; gain = 327.094
Finished Writing Synthesis Report : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 9 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 585.000 ; gain = 327.094
Synthesis Optimization Complete : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 585.000 ; gain = 327.094
Synthesis finished with 0 errors, 0 critical warnings and 6 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
Synthesis Optimization Complete : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 682.445 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00 . Memory (MB): peak = 683.723 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
INFO: [Common 17-83] Releasing license: Synthesis
100 Infos, 9 Warnings, 0 Critical Warnings and 0 Errors encountered.
80 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:23 . Memory (MB): peak = 682.445 ; gain = 424.539
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 682.445 ; gain = 0.000
synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 683.723 ; gain = 436.063
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 683.723 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.dcp' has been generated.
INFO: [Common 17-1381] The checkpoint 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Sat Apr 6 17:33:45 2019...
INFO: [Common 17-206] Exiting Vivado at Wed Apr 10 12:50:01 2019...

BIN
lab2CA.runs/synth_1/CPU9bits_tb.dcp
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BIN
lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.pb
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lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb
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28
lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.rpt → lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt
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@@ -1,8 +1,8 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Apr 6 17:33:45 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Date : Wed Apr 10 12:50:00 2019
| Host : WM-G75VW running 64-bit major release (build 9200)
| Command : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
| Design : CPU9bits
| Device : 7k160tifbg484-2L
@@ -30,11 +30,11 @@ Table of Contents
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs* | 54 | 0 | 101400 | 0.05 |
| LUT as Logic | 54 | 0 | 101400 | 0.05 |
| Slice LUTs* | 168 | 0 | 101400 | 0.17 |
| LUT as Logic | 168 | 0 | 101400 | 0.17 |
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
| Slice Registers | 58 | 0 | 202800 | 0.03 |
| Register as Flip Flop | 58 | 0 | 202800 | 0.03 |
| Slice Registers | 181 | 0 | 202800 | 0.09 |
| Register as Flip Flop | 181 | 0 | 202800 | 0.09 |
| Register as Latch | 0 | 0 | 202800 | 0.00 |
| F7 Muxes | 1 | 0 | 50700 | <0.01 |
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
@@ -57,7 +57,7 @@ Table of Contents
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 58 | Yes | Reset | - |
| 181 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
@@ -152,17 +152,17 @@ Table of Contents
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDRE | 58 | Flop & Latch |
| LUT4 | 23 | LUT |
| LUT3 | 17 | LUT |
| LUT5 | 11 | LUT |
| FDRE | 181 | Flop & Latch |
| LUT6 | 101 | LUT |
| LUT5 | 42 | LUT |
| LUT4 | 25 | LUT |
| LUT3 | 22 | LUT |
| OBUF | 10 | IO |
| LUT6 | 9 | LUT |
| LUT2 | 6 | LUT |
| LUT2 | 9 | LUT |
| LUT1 | 2 | LUT |
| IBUF | 2 | IO |
| RAMB18E1 | 1 | Block Memory |
| MUXF7 | 1 | MuxFx |
| LUT1 | 1 | LUT |
| BUFG | 1 | Clock |
+----------+------+---------------------+

10
lab2CA.runs/synth_1/gen_run.xml
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@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1554586396">
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1554914960">
<File Type="PA-TCL" Name="CPU9bits.tcl"/>
<File Type="RDS-PROPCONSTRS" Name="CPU9bits_drc_synth.rpt"/>
<File Type="REPORTS-TCL" Name="CPU9bits_reports.tcl"/>
@@ -96,14 +96,6 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../Downloads/pipeline_example.v">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="CPU9bits"/>

2
lab2CA.runs/synth_1/htr.txt
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@@ -6,4 +6,4 @@ REM to be invoked for Vivado to track run status.
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
REM
vivado -log CPU9bits_tb.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits_tb.tcl
vivado -log CPU9bits.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl

10
lab2CA.runs/synth_1/vivado.jou
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@@ -2,11 +2,11 @@
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sat Apr 6 17:33:19 2019
# Process ID: 7092
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1
# Start of session at: Wed Apr 10 12:49:25 2019
# Process ID: 13540
# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1
# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou
# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds
# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou
#-----------------------------------------------------------
source CPU9bits.tcl -notrace

BIN
lab2CA.runs/synth_1/vivado.pb
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Binary file not shown.

14
lab2CA.sim/sim_1/behav/xsim/webtalk.jou
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@@ -2,11 +2,11 @@
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sat Apr 6 17:41:26 2019
# Process ID: 2772
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
# Start of session at: Wed Apr 10 10:36:59 2019
# Process ID: 20220
# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace
source C:/REPOSITORIES/Educational/Western -notrace

12
lab2CA.sim/sim_1/behav/xsim/webtalk_11564.backup.jou
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@@ -1,12 +0,0 @@
#-----------------------------------------------------------
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sat Apr 6 13:16:30 2019
# Process ID: 11564
# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/REPOSITORIES/Educational/Western -notrace

12
lab2CA.sim/sim_1/behav/xsim/webtalk_2772.backup.jou Normal file
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@@ -0,0 +1,12 @@
#-----------------------------------------------------------
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sat Apr 6 17:41:26 2019
# Process ID: 2772
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace

12
lab2CA.sim/sim_1/behav/xsim/webtalk_28052.backup.jou
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@@ -1,12 +0,0 @@
#-----------------------------------------------------------
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Fri Mar 29 15:28:37 2019
# Process ID: 28052
# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/REPOSITORIES/Educational/Western -notrace

6
lab2CA.sim/sim_1/behav/xsim/webtalk_10700.backup.jou → lab2CA.sim/sim_1/behav/xsim/webtalk_3008.backup.jou
View File

@@ -2,10 +2,10 @@
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sat Apr 6 13:17:03 2019
# Process ID: 10700
# Start of session at: Wed Apr 10 10:36:10 2019
# Process ID: 3008
# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/xsim_webtalk.tcl -notrace
# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------

40
lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
View File

@@ -1,10 +1,10 @@
webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/
webtalk_init -webtalk_dir C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/
webtalk_register_client -client project
webtalk_add_data -client project -key date_generated -value "Sat Apr 6 17:49:44 2019" -context "software_version_and_target_device"
webtalk_add_data -client project -key date_generated -value "Wed Apr 10 12:50:20 2019" -context "software_version_and_target_device"
webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device"
webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device"
webtalk_add_data -client project -key registration_id -value "174150793_174150794_210688225_140" -context "software_version_and_target_device"
webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device"
webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device"
webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device"
webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device"
@@ -12,31 +12,21 @@ webtalk_add_data -client project -key target_family -value "not_applicable" -con
webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device"
webtalk_add_data -client project -key random_id -value "f67bb5263bf851bf9c1beaa84fe1017c" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "142" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "78" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment"
webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment"
webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user_environment"
webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-3630QM CPU @ 2.40GHz" -context "user_environment"
webtalk_add_data -client project -key cpu_speed -value "2395 MHz" -context "user_environment"
webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment"
webtalk_add_data -client project -key system_ram -value "17.000 GB" -context "user_environment"
webtalk_register_client -client xsim
webtalk_add_data -client xsim -key File_Counter -value "12" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Simulation_Image_Code -value "114 KB" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Image_Data -value "20 KB" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Processes -value "318" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Instances -value "149" -context "xsim\\usage"
webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip unimacro_ver unisims_ver " -context "xsim\\usage"
webtalk_add_data -client xsim -key Compiler_Time -value "0.89_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Compiler_Memory -value "46724_KB" -context "xsim\\usage"
webtalk_transmit -clientid 3689767801 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage"
webtalk_add_data -client xsim -key runtime -value "10065 ns" -context "xsim\\usage"
webtalk_add_data -client xsim -key iteration -value "3" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Time -value "0.09_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Memory -value "6280_KB" -context "xsim\\usage"
webtalk_transmit -clientid 722425617 -regid "" -xml C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_terminate

BIN
lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
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BIN
lab2CA.sim/sim_1/behav/xsim/xvlog.pb
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27
lab2CA.xpr
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@@ -3,7 +3,7 @@
<!-- -->
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="39" Path="C:/Users/ecelab/ECE3570-Lab/lab2CA.xpr">
<Project Version="7" Minor="39" Path="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="0a5803efda44405bb28bbf43ba22e808"/>
@@ -31,7 +31,7 @@
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="360"/>
<Option Name="WTXSimLaunchSim" Val="371"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@@ -162,11 +162,6 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/Bank_behav1.wcfg">
<FileInfo>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="CPU9bits_tb"/>
@@ -215,7 +210,7 @@
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k160tifbg484-2L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k160tifbg484-2L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
<Step Id="init_design"/>
@@ -228,11 +223,25 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
</Runs>
<MsgRule>
<MsgAttr Name="RuleType" Val="0"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="ANY"/>
<MsgAttr Name="Id" Val="Vivado 12-818"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="8"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="1"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="WARNING: [Vivado 12-818] No files matched &apos;C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/Bank_behav1.wcfg&apos;"/>
</MsgRule>
<Board/>
<DashboardSummary Version="1" Minor="0">
<Dashboards>