1462 lines
24 KiB
Verilog
1462 lines
24 KiB
Verilog
`timescale 1ns / 1ps
|
|
|
|
module add_1bit(
|
|
input wire A,
|
|
input wire B,
|
|
input wire Cin,
|
|
output wire S,
|
|
output wire Cout);
|
|
|
|
assign S = (A ^ B) ^ Cin;
|
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assign Cout = ((A ^ B) & Cin) | (A & B);
|
|
|
|
endmodule
|
|
|
|
//testbench
|
|
module add1bit_tb();
|
|
reg v;
|
|
reg w;
|
|
reg x;
|
|
wire y;
|
|
wire z;
|
|
|
|
add_1bit tb0(
|
|
.A(v),
|
|
.B(w),
|
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.Cin(x),
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|
.S(y),
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|
.Cout(z));
|
|
|
|
initial begin
|
|
v = 0;
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|
w = 0;
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x = 0;
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#5
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v = 0;
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w = 1;
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|
x = 0;
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#5
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v = 0;
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|
w = 0;
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x = 1;
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#5
|
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v = 1;
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w = 1;
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x = 0;
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#5
|
|
v = 1;
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|
w = 1;
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x = 1;
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#5
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$finish;
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|
|
|
end
|
|
endmodule
|
|
|
|
module add_9bit(
|
|
input wire [8:0] A,
|
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input wire [8:0] B,
|
|
input wire Cin,
|
|
output wire [8:0] Sum,
|
|
output wire Cout);
|
|
|
|
wire C_add0;
|
|
wire C_add1;
|
|
wire C_add2;
|
|
wire C_add3;
|
|
wire C_add4;
|
|
wire C_add5;
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wire C_add6;
|
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wire C_add7;
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|
|
|
add_1bit add0(
|
|
.A(A[0]),
|
|
.B(B[0]),
|
|
.Cin(Cin),
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|
.S(Sum[0]),
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.Cout(C_add0));
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|
|
|
add_1bit add1(
|
|
.A(A[1]),
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|
.B(B[1]),
|
|
.Cin(C_add0),
|
|
.S(Sum[1]),
|
|
.Cout(C_add1));
|
|
|
|
add_1bit add2(
|
|
.A(A[2]),
|
|
.B(B[2]),
|
|
.Cin(C_add1),
|
|
.S(Sum[2]),
|
|
.Cout(C_add2));
|
|
|
|
add_1bit add3(
|
|
.A(A[3]),
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|
.B(B[3]),
|
|
.Cin(C_add2),
|
|
.S(Sum[3]),
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|
.Cout(C_add3));
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|
|
|
add_1bit add4(
|
|
.A(A[4]),
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|
.B(B[4]),
|
|
.Cin(C_add3),
|
|
.S(Sum[4]),
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|
.Cout(C_add4));
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|
|
|
add_1bit add5(
|
|
.A(A[5]),
|
|
.B(B[5]),
|
|
.Cin(C_add4),
|
|
.S(Sum[5]),
|
|
.Cout(C_add5));
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|
|
|
add_1bit add6(
|
|
.A(A[6]),
|
|
.B(B[6]),
|
|
.Cin(C_add5),
|
|
.S(Sum[6]),
|
|
.Cout(C_add6));
|
|
|
|
add_1bit add7(
|
|
.A(A[7]),
|
|
.B(B[7]),
|
|
.Cin(C_add6),
|
|
.S(Sum[7]),
|
|
.Cout(C_add7));
|
|
|
|
add_1bit add8(
|
|
.A(A[8]),
|
|
.B(B[8]),
|
|
.Cin(C_add7),
|
|
.S(Sum[8]),
|
|
.Cout(Cout));
|
|
|
|
endmodule
|
|
|
|
//testbench
|
|
module add9bit_tb();
|
|
reg [8:0] a,b;
|
|
reg cin;
|
|
wire [8:0] s;
|
|
wire cout;
|
|
|
|
add_9bit tb0(
|
|
.A(a),
|
|
.B(b),
|
|
.Cin(cin),
|
|
.Sum(s),
|
|
.Cout(cout));
|
|
|
|
|
|
initial begin
|
|
a = 9'b000000000;
|
|
b = 9'b000000000;
|
|
cin = 0;
|
|
#5
|
|
a = 9'b000000001;
|
|
b = 9'b000000000;
|
|
cin = 0;
|
|
#5
|
|
a = 9'b000000000;
|
|
b = 9'b000000001;
|
|
cin = 1;
|
|
#5
|
|
a = 9'b000000001;
|
|
b = 9'b000000001;
|
|
cin = 0;
|
|
#5
|
|
a = 9'b000001000;
|
|
b = 9'b000000001;
|
|
cin = 1;
|
|
end
|
|
endmodule
|
|
|
|
module and_9bit(
|
|
input wire [8:0] A,
|
|
input wire [8:0] B,
|
|
output wire [8:0] C);
|
|
|
|
assign C = A & B;
|
|
|
|
endmodule
|
|
|
|
//testbench
|
|
module and9bit_tb();
|
|
reg [8:0] a,b;
|
|
wire [8:0] c;
|
|
|
|
and_9bit and0(
|
|
.A(a),
|
|
.B(b),
|
|
.C(c));
|
|
|
|
initial begin
|
|
a = 9'b000000000;
|
|
b = 9'b000000000;
|
|
#5
|
|
a = 9'b000000000;
|
|
b = 9'b000000001;
|
|
#5
|
|
a = 9'b000000001;
|
|
b = 9'b000000000;
|
|
#5
|
|
a = 9'b000000001;
|
|
b = 9'b000000001;
|
|
#5
|
|
a = 9'b000100001;
|
|
b = 9'b000000001;
|
|
#5
|
|
a = 9'b000100001;
|
|
b = 9'b000100001;
|
|
#5
|
|
$finish;
|
|
|
|
end
|
|
endmodule
|
|
|
|
module comparator (
|
|
input wire [8:0] A,
|
|
input wire [8:0] B,
|
|
output wire [8:0] C);
|
|
|
|
assign C = (~A & ~B) | (A & B);
|
|
|
|
endmodule
|
|
|
|
//testbench
|
|
module comparator_tb();
|
|
reg [8:0] a,b;
|
|
wire [8:0] c;
|
|
|
|
comparator comparator0(
|
|
.A(a),
|
|
.B(b),
|
|
.C(c));
|
|
|
|
initial begin
|
|
a = 9'b000000000;
|
|
b = 9'b000000000;
|
|
#5
|
|
a = 9'b000000000;
|
|
b = 9'b000000001;
|
|
#5
|
|
a = 9'b000000001;
|
|
b = 9'b000000000;
|
|
#5
|
|
a = 9'b000000001;
|
|
b = 9'b000000001;
|
|
#5
|
|
a = 9'b000100001;
|
|
b = 9'b000000001;
|
|
#5
|
|
a = 9'b000100001;
|
|
b = 9'b000100001;
|
|
#5
|
|
$finish;
|
|
|
|
end
|
|
endmodule
|
|
|
|
module decoder (
|
|
input wire [1:0] index,
|
|
input wire En,
|
|
output reg [3:0] regOut);
|
|
|
|
always @ (index, En)
|
|
if (En == 0) begin
|
|
case(index)
|
|
2'b00: regOut <= 4'b1110;
|
|
2'b01: regOut <= 4'b1101;
|
|
2'b10: regOut <= 4'b1011;
|
|
2'b11: regOut <= 4'b0111;
|
|
default: regOut <= 4'b1111;
|
|
endcase
|
|
end
|
|
else begin
|
|
regOut <= 4'b1111;
|
|
end
|
|
|
|
endmodule
|
|
|
|
//testbench
|
|
module decoder_tb();
|
|
reg [1:0] indexIn;
|
|
wire [3:0] regOut;
|
|
|
|
decoder dec0(
|
|
.index(indexIn),
|
|
.regOut(regOut)
|
|
);
|
|
|
|
initial begin
|
|
indexIn = 2'b00;
|
|
#5
|
|
indexIn = 2'b01;
|
|
#5
|
|
indexIn = 2'b10;
|
|
#5
|
|
indexIn = 2'b11;
|
|
#5
|
|
$finish;
|
|
|
|
end
|
|
endmodule
|
|
|
|
module gen_clock();
|
|
reg clk;
|
|
initial begin
|
|
clk = 1'b0;
|
|
end
|
|
always begin
|
|
#5 clk = ~clk; // Period to be determined
|
|
end
|
|
endmodule
|
|
|
|
module less_than(
|
|
input wire [8:0] A,B,
|
|
output wire [8:0] C);
|
|
|
|
wire [8:0] D;
|
|
|
|
sub_9bit sub0(
|
|
.A(A),
|
|
.B(B),
|
|
.C(D));
|
|
|
|
assign C = {8'b00000000,D[8]};
|
|
// 1 if A is less than B
|
|
// 0 if B is greater than or equal to A
|
|
endmodule
|
|
|
|
module mux_2_1(
|
|
input wire switch,
|
|
input wire [8:0] A,B,
|
|
output reg [8:0] out);
|
|
|
|
always @(A,B,switch) begin
|
|
case (switch)
|
|
1'b0 : out = A;
|
|
1'b1 : out = B;
|
|
default : out = 9'bxxxxxxxxx;
|
|
endcase
|
|
end
|
|
endmodule
|
|
|
|
module bit1_mux_2_1(
|
|
input wire switch,
|
|
input wire A,B,
|
|
output reg out);
|
|
|
|
always @(A,B,switch) begin
|
|
case (switch)
|
|
1'b0 : out = A;
|
|
1'b1 : out = B;
|
|
default : out = 1'b1;
|
|
endcase
|
|
end
|
|
endmodule
|
|
|
|
|
|
//testbench
|
|
module mux_2_1_tb();
|
|
reg s;
|
|
reg [8:0] a,b;
|
|
wire [8:0] c;
|
|
|
|
mux_2_1 tb0(
|
|
.switch(s),
|
|
.A(a),
|
|
.B(b),
|
|
.out(c));
|
|
|
|
initial begin
|
|
s = 0;
|
|
a = 9'b000000101;
|
|
b = 9'b000000000;
|
|
#5
|
|
s = 1;
|
|
a = 9'b000000001;
|
|
b = 9'b000100001;
|
|
#5
|
|
s = 0;
|
|
a = 9'b000000000;
|
|
b = 9'b000000001;
|
|
#5
|
|
s = 1;
|
|
a = 9'b000000001;
|
|
b = 9'b000000001;
|
|
#5
|
|
s = 0;
|
|
a = 9'b000010001;
|
|
b = 9'b000000001;
|
|
#5
|
|
s = 1;
|
|
a = 9'b000010001;
|
|
b = 9'b000010111;
|
|
#5
|
|
$finish;
|
|
|
|
end
|
|
endmodule
|
|
|
|
module mux_4_1(input wire [1:0] switch,
|
|
input wire [8:0] A,B,C,D,
|
|
output reg [8:0] out);
|
|
|
|
always @(A,B,C,D,switch) begin
|
|
case (switch)
|
|
2'b00 : out = A;
|
|
2'b01 : out = B;
|
|
2'b10 : out = C;
|
|
2'b11 : out = D;
|
|
default : out = 9'bxxxxxxxxx;
|
|
endcase
|
|
end
|
|
|
|
endmodule
|
|
|
|
//testbench
|
|
module mux_4_1_tb();
|
|
reg [1:0] s;
|
|
reg [8:0] a,b,c,d;
|
|
wire [8:0] e;
|
|
|
|
mux_4_1 tb0(
|
|
.switch(s),
|
|
.A(a),
|
|
.B(b),
|
|
.C(c),
|
|
.D(d),
|
|
.out(e));
|
|
|
|
initial begin
|
|
s = 2'b00;
|
|
a = 9'b000000101;
|
|
b = 9'b000111100;
|
|
c = 9'b001001001;
|
|
d = 9'b100000000;
|
|
#5
|
|
s = 2'b01;
|
|
a = 9'b000000101;
|
|
b = 9'b000111100;
|
|
c = 9'b001001001;
|
|
d = 9'b100000000;
|
|
#5
|
|
s = 2'b10;
|
|
a = 9'b000000101;
|
|
b = 9'b000111100;
|
|
c = 9'b001001001;
|
|
d = 9'b100000000;
|
|
#5
|
|
s = 2'b11;
|
|
a = 9'b000000101;
|
|
b = 9'b000111100;
|
|
c = 9'b001001001;
|
|
d = 9'b100000000;
|
|
#5
|
|
$finish;
|
|
|
|
end
|
|
endmodule
|
|
|
|
module mux_8_1(
|
|
input wire [2:0] switch,
|
|
input wire [8:0] A,B,C,D,E,F,G,H,
|
|
output reg [8:0] out);
|
|
|
|
always @(A,B,C,D,E,F,G,H,switch) begin
|
|
case (switch)
|
|
3'b000 : out = A;
|
|
3'b001 : out = B;
|
|
3'b010 : out = C;
|
|
3'b011 : out = D;
|
|
3'b100 : out = E;
|
|
3'b101 : out = F;
|
|
3'b110 : out = G;
|
|
3'b111 : out = H;
|
|
default : out = 9'bxxxxxxxxx;
|
|
endcase
|
|
end
|
|
endmodule
|
|
|
|
//testbench
|
|
module mux_8_1_tb();
|
|
reg [2:0] s;
|
|
reg [8:0] a,b,c,d,e,f,g,h;
|
|
wire [8:0] out;
|
|
|
|
mux_8_1 tb0(
|
|
.switch(s),
|
|
.A(a),
|
|
.B(b),
|
|
.C(c),
|
|
.D(d),
|
|
.E(e),
|
|
.F(f),
|
|
.G(g),
|
|
.H(h),
|
|
.out(out));
|
|
|
|
initial begin
|
|
s = 3'b000;
|
|
a = 9'b000000101;
|
|
b = 9'b000111100;
|
|
c = 9'b001001001;
|
|
d = 9'b100110000;
|
|
e = 9'b010000101;
|
|
f = 9'b010111100;
|
|
g = 9'b011001001;
|
|
h = 9'b111000000;
|
|
#5
|
|
s = 3'b001;
|
|
#5
|
|
s = 3'b010;
|
|
#5
|
|
s = 3'b011;
|
|
#5
|
|
s = 3'b100;
|
|
#5
|
|
s = 3'b101;
|
|
#5
|
|
s = 3'b110;
|
|
#5
|
|
s = 3'b111;
|
|
#5
|
|
$finish;
|
|
|
|
end
|
|
endmodule
|
|
|
|
module mux_16_1(
|
|
input wire [3:0] switch,
|
|
input wire [8:0] A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P,
|
|
output reg [8:0] out);
|
|
|
|
always @(A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P,switch) begin
|
|
case (switch)
|
|
4'b0000 : out = A;
|
|
4'b0001 : out = B;
|
|
4'b0010 : out = C;
|
|
4'b0011 : out = D;
|
|
4'b0100 : out = E;
|
|
4'b0101 : out = F;
|
|
4'b0110 : out = G;
|
|
4'b0111 : out = H;
|
|
4'b1000 : out = I;
|
|
4'b1001 : out = J;
|
|
4'b1010 : out = K;
|
|
4'b1011 : out = L;
|
|
4'b1100 : out = M;
|
|
4'b1101 : out = N;
|
|
4'b1110 : out = O;
|
|
4'b1111 : out = P;
|
|
default : out = 9'bxxxxxxxxx;
|
|
endcase
|
|
end
|
|
endmodule
|
|
|
|
//testbench
|
|
module mux_16_1_tb();
|
|
reg [2:0] switch;
|
|
reg [8:0] a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p;
|
|
wire [8:0] out;
|
|
|
|
mux_16_1 tb0(
|
|
.switch(switch),
|
|
.A(a),
|
|
.B(b),
|
|
.C(c),
|
|
.D(d),
|
|
.E(e),
|
|
.F(f),
|
|
.G(g),
|
|
.H(h),
|
|
.I(i),
|
|
.J(j),
|
|
.K(k),
|
|
.L(l),
|
|
.M(m),
|
|
.N(n),
|
|
.O(o),
|
|
.P(p),
|
|
.out(out));
|
|
|
|
initial begin
|
|
switch = 4'b0000;
|
|
a = 9'b000000101;
|
|
b = 9'b000111100;
|
|
c = 9'b001001001;
|
|
d = 9'b100110000;
|
|
e = 9'b010000101;
|
|
f = 9'b010111100;
|
|
g = 9'b011001001;
|
|
h = 9'b111000000;
|
|
i = 9'b100100101;
|
|
j = 9'b000001100;
|
|
k = 9'b001001001;
|
|
l = 9'b100110011;
|
|
m = 9'b010111101;
|
|
n = 9'b010110100;
|
|
o = 9'b100101001;
|
|
p = 9'b111001100;
|
|
#5
|
|
switch = 4'b0001;
|
|
#5
|
|
switch = 4'b0010;
|
|
#5
|
|
switch = 4'b0011;
|
|
#5
|
|
switch = 4'b0100;
|
|
#5
|
|
switch = 4'b0101;
|
|
#5
|
|
switch = 4'b0110;
|
|
#5
|
|
switch = 4'b0111;
|
|
#5
|
|
switch = 4'b1000;
|
|
#5
|
|
switch = 4'b1001;
|
|
#5
|
|
switch = 4'b1010;
|
|
#5
|
|
switch = 4'b1011;
|
|
#5
|
|
switch = 4'b1100;
|
|
#5
|
|
switch = 4'b1101;
|
|
#5
|
|
switch = 4'b1110;
|
|
#5
|
|
switch = 4'b1111;
|
|
#5
|
|
$finish;
|
|
|
|
end
|
|
endmodule
|
|
|
|
module nor_9bit(
|
|
input wire [8:0] A,
|
|
input wire [8:0] B,
|
|
output wire [8:0] C);
|
|
|
|
assign C = ~(A | B);
|
|
|
|
endmodule
|
|
|
|
//testbench
|
|
module nor_9bit_tb();
|
|
reg [8:0] a;
|
|
reg [8:0] b;
|
|
wire [8:0] c;
|
|
|
|
nor_9bit nor0(
|
|
.A(a),
|
|
.B(b),
|
|
.C(c));
|
|
|
|
initial begin
|
|
a = 9'b000000000;
|
|
b = 9'b000000000;
|
|
#5
|
|
a = 9'b000000000;
|
|
b = 9'b000000001;
|
|
#5
|
|
a = 9'b000000001;
|
|
b = 9'b000000000;
|
|
#5
|
|
a = 9'b000000001;
|
|
b = 9'b000000001;
|
|
#5
|
|
a = 9'b000100001;
|
|
b = 9'b000000001;
|
|
#5
|
|
a = 9'b000100001;
|
|
b = 9'b000100001;
|
|
#5
|
|
$finish;
|
|
|
|
end
|
|
endmodule
|
|
|
|
module not_9bit(
|
|
input wire [8:0] A,
|
|
output wire [8:0] B);
|
|
|
|
assign B = ~A;
|
|
|
|
endmodule
|
|
|
|
//testbench
|
|
module not_9bit_tb();
|
|
reg [8:0] a;
|
|
wire [8:0] b;
|
|
|
|
not_9bit not0(
|
|
.A(a),
|
|
.B(b));
|
|
|
|
initial begin
|
|
a = 9'b000000000;
|
|
#5
|
|
a = 9'b000000001;
|
|
#5
|
|
a = 9'b000111000;
|
|
#5
|
|
a = 9'b010101010;
|
|
#5
|
|
a = 9'b101010101;
|
|
#5
|
|
a = 9'b111111111;
|
|
#5
|
|
a = 9'b100000001;
|
|
#5
|
|
$finish;
|
|
|
|
end
|
|
endmodule
|
|
|
|
module or_9bit(
|
|
input wire [8:0] A,
|
|
input wire [8:0] B,
|
|
output wire [8:0] C);
|
|
|
|
assign C = A | B;
|
|
|
|
endmodule
|
|
|
|
//testbench
|
|
module or_9bit_tb();
|
|
reg [8:0] a;
|
|
reg [8:0] b;
|
|
wire [8:0] c;
|
|
|
|
or_9bit tb0(
|
|
.A(a),
|
|
.B(b),
|
|
.C(c));
|
|
|
|
initial begin
|
|
a = 9'b000000000;
|
|
b = 9'b000000000;
|
|
#5
|
|
a = 9'b111111111;
|
|
b = 9'b111111111;
|
|
#5
|
|
a = 9'b111111111;
|
|
b = 9'b000000000;
|
|
#5
|
|
a = 9'b000000000;
|
|
b = 9'b111111111;
|
|
#5
|
|
a = 9'b000000000;
|
|
b = 9'b111111111;
|
|
#5
|
|
a = 9'b010101010;
|
|
b = 9'b111111111;
|
|
#5
|
|
a = 9'b010101010;
|
|
b = 9'b101010101;
|
|
#5
|
|
a = 9'b000011111;
|
|
b = 9'b111111111;
|
|
#5
|
|
a = 9'b000000000;
|
|
b = 9'b000010000;
|
|
#5
|
|
$finish;
|
|
|
|
end
|
|
endmodule
|
|
|
|
module register(
|
|
input wire clk, reset,
|
|
input wire En,
|
|
input wire [8:0] Din,
|
|
output reg [8:0] Dout);
|
|
|
|
always @(posedge clk) begin
|
|
if (reset == 1'b1) begin
|
|
Dout <= 9'b000000000;
|
|
end
|
|
else if (En == 1'b0) begin
|
|
Dout = Din;
|
|
end
|
|
else begin
|
|
Dout = Dout;
|
|
end
|
|
end
|
|
endmodule
|
|
|
|
//testbench
|
|
module register_tb();
|
|
reg clk,reset;
|
|
reg [1:0] En;
|
|
reg [8:0] Din;
|
|
wire [8:0] Dout;
|
|
|
|
register tb0(
|
|
.clk(clk),
|
|
.reset(reset),
|
|
.En(En),
|
|
.Din(Din),
|
|
.Dout(Dout));
|
|
|
|
initial begin
|
|
clk = 0;
|
|
reset = 0;
|
|
En = 2'b00;
|
|
Din = 9'b000000000;
|
|
#5
|
|
clk = 1;
|
|
#5
|
|
clk = 0;
|
|
reset = 0;
|
|
En = 2'b00;
|
|
Din = 9'b010101010;
|
|
#5
|
|
clk = 1;
|
|
#5
|
|
clk = 0;
|
|
reset = 1;
|
|
En = 2'b00;
|
|
Din = 9'b010101010;
|
|
#5
|
|
clk = 1;
|
|
#5
|
|
clk = 0;
|
|
reset = 0;
|
|
En = 2'b01;
|
|
Din = 9'b101010101;
|
|
#5
|
|
clk = 1;
|
|
#5
|
|
clk = 0;
|
|
reset = 0;
|
|
En = 2'b00;
|
|
Din = 9'b000011111;
|
|
#5
|
|
clk = 1;
|
|
#5
|
|
clk = 0;
|
|
#5
|
|
$finish;
|
|
|
|
end
|
|
endmodule
|
|
|
|
module fDPipReg(
|
|
input wire clk,
|
|
input wire reset,
|
|
input wire En,
|
|
input wire [52:0] Din,
|
|
output reg [52:0] Dout);
|
|
|
|
always @(posedge clk) begin
|
|
if (reset == 1'b1) begin
|
|
Dout <= 50'b00000000000000000000000000000000000000000000000000;
|
|
end
|
|
else if (En == 1'b0) begin
|
|
Dout <= Din;
|
|
end
|
|
end
|
|
endmodule
|
|
|
|
module eMPipReg(
|
|
input wire clk,
|
|
input wire reset,
|
|
input wire En,
|
|
input wire [61:0] Din,
|
|
output reg [61:0] Dout);
|
|
|
|
always @(posedge clk) begin
|
|
if (reset == 1'b1) begin
|
|
Dout <= 60'b0000000000000000000000000000000000000000000000000000000000000000000000;
|
|
end
|
|
else if (En == 1'b0) begin
|
|
Dout <= Din;
|
|
end
|
|
end
|
|
endmodule
|
|
|
|
module shift_left(
|
|
input wire [7:0] A,
|
|
output wire [8:0] B);
|
|
|
|
assign B = {A[7:0],1'b0};
|
|
|
|
endmodule
|
|
|
|
//testbench
|
|
module shift_left_tb();
|
|
reg [8:0] a;
|
|
wire [8:0] b;
|
|
|
|
shift_left tb0(
|
|
.A(a),
|
|
.B(b));
|
|
|
|
initial begin
|
|
a = 9'b000000000;
|
|
#5
|
|
a = 9'b000000001;
|
|
#5
|
|
a = 9'b000111000;
|
|
#5
|
|
a = 9'b010101010;
|
|
#5
|
|
a = 9'b101010101;
|
|
#5
|
|
a = 9'b111111111;
|
|
#5
|
|
a = 9'b100000001;
|
|
#5
|
|
$finish;
|
|
|
|
end
|
|
endmodule
|
|
|
|
module shift_right_arithmetic(
|
|
input wire [8:1] A,
|
|
output wire [8:0] B);
|
|
|
|
assign B = {A[8],A[8:1]};
|
|
|
|
endmodule
|
|
|
|
//testbench
|
|
module shift_right_arithmetic_tb();
|
|
reg [8:0] a;
|
|
wire [8:0] b;
|
|
|
|
shift_right_arithmetic tb0(
|
|
.A(a),
|
|
.B(b));
|
|
|
|
initial begin
|
|
a = 9'b000000000;
|
|
#5
|
|
a = 9'b000000001;
|
|
#5
|
|
a = 9'b000111000;
|
|
#5
|
|
a = 9'b010101010;
|
|
#5
|
|
a = 9'b101010101;
|
|
#5
|
|
a = 9'b111111111;
|
|
#5
|
|
a = 9'b100000001;
|
|
#5
|
|
$finish;
|
|
|
|
end
|
|
endmodule
|
|
|
|
module shift_right_logical(
|
|
input wire [8:1] A,
|
|
output wire [8:0] B);
|
|
|
|
assign B = {1'b0,A[8:1]};
|
|
|
|
|
|
endmodule
|
|
|
|
//testbench
|
|
module shift_right_logical_tb();
|
|
reg [8:0] a;
|
|
wire [8:0] b;
|
|
|
|
shift_right_logical tb0(
|
|
.A(a),
|
|
.B(b));
|
|
|
|
initial begin
|
|
a = 9'b000000000;
|
|
#5
|
|
a = 9'b000000001;
|
|
#5
|
|
a = 9'b000111000;
|
|
#5
|
|
a = 9'b010101010;
|
|
#5
|
|
a = 9'b101010101;
|
|
#5
|
|
a = 9'b111111111;
|
|
#5
|
|
a = 9'b100000001;
|
|
#5
|
|
$finish;
|
|
|
|
end
|
|
endmodule
|
|
|
|
module sign_extend_2bit(
|
|
input wire [1:0] A,
|
|
output wire [8:0] B);
|
|
|
|
assign B = {{7{A[1]}},A};
|
|
|
|
endmodule
|
|
|
|
//testbench
|
|
module sign_extend_2bit_tb();
|
|
reg [1:0] A;
|
|
wire [8:0] B;
|
|
|
|
sign_extend_2bit tb0(
|
|
.A(A),
|
|
.B(B));
|
|
|
|
initial begin
|
|
A = 2'b00;
|
|
#5
|
|
A = 2'b01;
|
|
#5
|
|
A = 2'b10;
|
|
#5
|
|
A = 2'b11;
|
|
#5
|
|
$finish;
|
|
|
|
end
|
|
endmodule
|
|
|
|
module sign_extend_3bit(
|
|
input wire [2:0] A,
|
|
output wire [8:0] B);
|
|
|
|
assign B = {{6{A[2]}},A};
|
|
|
|
endmodule
|
|
|
|
//testbench
|
|
module sign_extend_3bit_tb();
|
|
reg [2:0] A;
|
|
wire [8:0] B;
|
|
|
|
sign_extend_3bit tb0(
|
|
.A(A),
|
|
.B(B));
|
|
|
|
initial begin
|
|
A = 3'b000;
|
|
#5
|
|
A = 3'b001;
|
|
#5
|
|
A = 3'b010;
|
|
#5
|
|
A = 3'b011;
|
|
#5
|
|
A = 3'b100;
|
|
#5
|
|
A = 3'b101;
|
|
#5
|
|
A = 3'b110;
|
|
#5
|
|
A = 3'b111;
|
|
#5
|
|
$finish;
|
|
|
|
end
|
|
endmodule
|
|
|
|
module sign_extend_4bit(
|
|
input wire [3:0] A,
|
|
output wire [8:0] B);
|
|
|
|
assign B = {{5{A[3]}},A};
|
|
|
|
endmodule
|
|
|
|
//testbench
|
|
module sign_extend_4bit_tb();
|
|
reg [3:0] A;
|
|
wire [8:0] B;
|
|
|
|
sign_extend_4bit tb0(
|
|
.A(A),
|
|
.B(B));
|
|
|
|
initial begin
|
|
A = 4'b0000;
|
|
#5
|
|
A = 4'b0001;
|
|
#5
|
|
A = 4'b0010;
|
|
#5
|
|
A = 4'b0011;
|
|
#5
|
|
A = 4'b0100;
|
|
#5
|
|
A = 4'b0101;
|
|
#5
|
|
A = 4'b0110;
|
|
#5
|
|
A = 4'b0111;
|
|
#5
|
|
A = 4'b1000;
|
|
#5
|
|
A = 4'b1001;
|
|
#5
|
|
A = 4'b1010;
|
|
#5
|
|
A = 4'b1011;
|
|
#5
|
|
A = 4'b1100;
|
|
#5
|
|
A = 4'b1101;
|
|
#5
|
|
A = 4'b1110;
|
|
#5
|
|
A = 4'b1111;
|
|
#5
|
|
$finish;
|
|
|
|
end
|
|
endmodule
|
|
|
|
module sign_extend_5bit(
|
|
input wire [4:0] A,
|
|
output wire [8:0] B);
|
|
|
|
assign B = {{4{A[4]}},A};
|
|
|
|
endmodule
|
|
|
|
//testbench
|
|
module sign_extend_5bit_tb();
|
|
reg [4:0] A;
|
|
wire [8:0] B;
|
|
|
|
sign_extend_5bit tb0(
|
|
.A(A),
|
|
.B(B));
|
|
|
|
initial begin
|
|
A = 5'b00000;
|
|
#5
|
|
A = 5'b00010;
|
|
#5
|
|
A = 5'b00100;
|
|
#5
|
|
A = 5'b00110;
|
|
#5
|
|
A = 5'b01000;
|
|
#5
|
|
A = 5'b01010;
|
|
#5
|
|
A = 5'b01100;
|
|
#5
|
|
A = 5'b01110;
|
|
#5
|
|
A = 5'b10000;
|
|
#5
|
|
A = 5'b10010;
|
|
#5
|
|
A = 5'b10100;
|
|
#5
|
|
A = 5'b10110;
|
|
#5
|
|
A = 5'b11000;
|
|
#5
|
|
A = 5'b11010;
|
|
#5
|
|
A = 5'b11100;
|
|
#5
|
|
A = 5'b11110;
|
|
#5
|
|
$finish;
|
|
|
|
end
|
|
endmodule
|
|
|
|
module sign_extend_6bit(
|
|
input wire [5:0] A,
|
|
output wire [8:0] B);
|
|
|
|
assign B = {{3{A[5]}},A};
|
|
|
|
endmodule
|
|
|
|
//testbench
|
|
module sign_extend_6bit_tb();
|
|
reg [5:0] A;
|
|
wire [8:0] B;
|
|
|
|
sign_extend_6bit tb0(
|
|
.A(A),
|
|
.B(B));
|
|
|
|
initial begin
|
|
A = 6'b000000;
|
|
#5
|
|
A = 6'b000100;
|
|
#5
|
|
A = 6'b001000;
|
|
#5
|
|
A = 6'b001100;
|
|
#5
|
|
A = 6'b010000;
|
|
#5
|
|
A = 6'b010100;
|
|
#5
|
|
A = 6'b011000;
|
|
#5
|
|
A = 6'b011100;
|
|
#5
|
|
A = 6'b100000;
|
|
#5
|
|
A = 6'b100100;
|
|
#5
|
|
A = 6'b101000;
|
|
#5
|
|
A = 6'b101100;
|
|
#5
|
|
A = 6'b110000;
|
|
#5
|
|
A = 6'b110100;
|
|
#5
|
|
A = 6'b111000;
|
|
#5
|
|
A = 6'b111100;
|
|
#5
|
|
$finish;
|
|
|
|
end
|
|
endmodule
|
|
|
|
module sign_extend_7bit(
|
|
input wire [6:0] A,
|
|
output wire [8:0] B);
|
|
|
|
assign B = {{2{A[6]}},A};
|
|
|
|
endmodule
|
|
|
|
//testbench
|
|
module sign_extend_7bit_tb();
|
|
reg [6:0] A;
|
|
wire [8:0] B;
|
|
|
|
sign_extend_7bit tb0(
|
|
.A(A),
|
|
.B(B));
|
|
|
|
initial begin
|
|
A = 7'b0000000;
|
|
#5
|
|
A = 7'b0001000;
|
|
#5
|
|
A = 7'b0010000;
|
|
#5
|
|
A = 7'b0011000;
|
|
#5
|
|
A = 7'b0100000;
|
|
#5
|
|
A = 7'b0101000;
|
|
#5
|
|
A = 7'b0110000;
|
|
#5
|
|
A = 7'b0111000;
|
|
#5
|
|
A = 7'b1000000;
|
|
#5
|
|
A = 7'b1001000;
|
|
#5
|
|
A = 7'b1010000;
|
|
#5
|
|
A = 7'b1011000;
|
|
#5
|
|
A = 7'b1100000;
|
|
#5
|
|
A = 7'b1101000;
|
|
#5
|
|
A = 7'b1110000;
|
|
#5
|
|
A = 7'b1111000;
|
|
#5
|
|
$finish;
|
|
|
|
end
|
|
endmodule
|
|
|
|
module sign_extend_8bit(
|
|
input wire [7:0] A,
|
|
output wire [8:0] B);
|
|
|
|
assign B = {A[7],A};
|
|
|
|
endmodule
|
|
|
|
//testbench
|
|
module sign_extend_8bit_tb();
|
|
reg [7:0] A;
|
|
wire [8:0] B;
|
|
|
|
sign_extend_8bit tb0(
|
|
.A(A),
|
|
.B(B));
|
|
|
|
initial begin
|
|
A = 8'b00000000;
|
|
#5
|
|
A = 8'b00010000;
|
|
#5
|
|
A = 8'b00100000;
|
|
#5
|
|
A = 8'b00110000;
|
|
#5
|
|
A = 8'b01000000;
|
|
#5
|
|
A = 8'b01010000;
|
|
#5
|
|
A = 8'b01100000;
|
|
#5
|
|
A = 8'b01110000;
|
|
#5
|
|
A = 8'b10000000;
|
|
#5
|
|
A = 8'b10010000;
|
|
#5
|
|
A = 8'b10100000;
|
|
#5
|
|
A = 8'b10110000;
|
|
#5
|
|
A = 8'b11000000;
|
|
#5
|
|
A = 8'b11010000;
|
|
#5
|
|
A = 8'b11100000;
|
|
#5
|
|
A = 8'b11110000;
|
|
#5
|
|
$finish;
|
|
|
|
end
|
|
endmodule
|
|
|
|
|
|
module sub_9bit(
|
|
input wire [8:0] A,
|
|
input wire [8:0] B,
|
|
output wire [8:0] C);
|
|
|
|
wire [8:0] D;
|
|
wire cout;
|
|
|
|
twos_compliment_9bit two_comp0(
|
|
.A(B),
|
|
.B(D));
|
|
|
|
add_9bit add0(
|
|
.A(A),
|
|
.B(D),
|
|
.Cin(1'b0),
|
|
.Sum(C),
|
|
.Cout(cout));
|
|
|
|
endmodule
|
|
|
|
//testbench
|
|
module sub_9bit_tb();
|
|
reg [8:0] a;
|
|
reg [8:0] b;
|
|
wire [8:0] c;
|
|
|
|
sub_9bit tb0(
|
|
.A(a),
|
|
.B(b),
|
|
.C(c));
|
|
|
|
initial begin
|
|
a = 9'b000000000;
|
|
b = 9'b000000000;
|
|
#5
|
|
a = 9'b111111111;
|
|
b = 9'b111111111;
|
|
#5
|
|
a = 9'b111111111;
|
|
b = 9'b000000000;
|
|
#5
|
|
a = 9'b000000000;
|
|
b = 9'b111111111;
|
|
#5
|
|
a = 9'b000000000;
|
|
b = 9'b111111111;
|
|
#5
|
|
a = 9'b010101010;
|
|
b = 9'b111111111;
|
|
#5
|
|
a = 9'b010101010;
|
|
b = 9'b101010101;
|
|
#5
|
|
a = 9'b000011111;
|
|
b = 9'b111111111;
|
|
#5
|
|
a = 9'b000000000;
|
|
b = 9'b000010000;
|
|
#5
|
|
$finish;
|
|
|
|
end
|
|
endmodule
|
|
|
|
module twos_compliment_9bit(
|
|
input wire [8:0] A,
|
|
output wire [8:0] B);
|
|
|
|
wire [8:0] C;
|
|
wire cout;
|
|
|
|
not_9bit not0(
|
|
.A(A),
|
|
.B(C));
|
|
|
|
add_9bit add0(
|
|
.A(C),
|
|
.B(9'b000000000),
|
|
.Cin(1'b1),
|
|
.Sum(B),
|
|
.Cout(cout));
|
|
|
|
endmodule
|
|
|
|
//testbench
|
|
module twos_compliment_tb();
|
|
reg [8:0] a;
|
|
wire [8:0] b;
|
|
|
|
twos_compliment_9bit tb0(
|
|
.A(a),
|
|
.B(b));
|
|
|
|
initial begin
|
|
a = 9'b000000000;
|
|
#5
|
|
a = 9'b000000001;
|
|
#5
|
|
a = 9'b000111000;
|
|
#5
|
|
a = 9'b010101010;
|
|
#5
|
|
a = 9'b101010101;
|
|
#5
|
|
a = 9'b111111111;
|
|
#5
|
|
a = 9'b100000001;
|
|
#5
|
|
$finish;
|
|
|
|
end
|
|
endmodule
|
|
|
|
module BEQ(
|
|
input wire [8:0] A,
|
|
output wire [8:0] B);
|
|
|
|
assign B = {8'b00000000, A[8] | A[7] | A[6] | A[5] | A[4] | A[3] | A[2] | A[1] | A[0]};
|
|
// 0 if zero
|
|
// 1 if non-zero
|
|
endmodule |