81 lines
1.8 KiB
Verilog
81 lines
1.8 KiB
Verilog
`timescale 1ns / 1ps
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module WMUdule(
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input wire [61:0] PipIn,
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output wire [8:0] RFIn,FUAddr,
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output wire [1:0] instr,
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output wire fetchBranch, RegEn
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);
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wire [8:0] PCout,AddiOut,AluOut,dataMemOut,bankOP,loadMux,linkData,bankData;
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wire addiS,loadS,link,bankS;
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assign RegEn = PipIn[61];
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assign PCout = PipIn[60:52];
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assign bankOP = PipIn[51:43];
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assign FUAddr = PipIn[42:34];
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assign AluOut = PipIn[33:25];
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assign dataMemOut = PipIn[24:16];
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assign AddiOut = PipIn[15:7];
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assign instr = PipIn[6:5];
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assign bankS = PipIn[4];
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assign loadS = PipIn[3];
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assign link = PipIn[2];
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assign addiS = PipIn[1];
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assign fetchBranch = PipIn[0];
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mux_2_1 mux3(
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.A(AluOut),
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.B(AddiOut),
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.out(loadMux),
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.switch(addiS)
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);
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mux_2_1 mux4(
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.A(linkData),
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.B(dataMemOut), // This is DATA MEM
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.out(bankData),
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.switch(loadS)
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);
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///--------------------------Bank stuff
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mux_2_1 mux5(
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.A(bankData),
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.B(bankOP),
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.out(RFIn),
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.switch(bankS)
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);
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///--------------------------Link Stuff
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mux_2_1 mux6(
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.A(loadMux),
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.B(PCout),
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.out(linkData),
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.switch(link)
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);
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endmodule
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//module WMUdule_tb();
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// reg [61:0] PipIn;
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// wire [8:0] RFIn,FUAddr;
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// wire [1:0] instr;
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// wire fetchBranch, RegEn;
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// WMUdule WMUdule_0(
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// .PipIn(PipIn),
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// .RFIn(RFIn),
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// .FUAddr(FUAddr),
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// .instr(instr),
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// .fetchBranch(fetchBranch),
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// .RegEn(RegEn)
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// );
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// initial begin
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// PipIn = 1;
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// #5
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// $finish;
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// end
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//endmodule
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