381 lines
20 KiB
Plaintext
381 lines
20 KiB
Plaintext
#-----------------------------------------------------------
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# Vivado v2018.3 (64-bit)
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# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
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# Start of session at: Wed Mar 13 11:12:42 2019
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# Process ID: 11884
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# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1
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# Command line: vivado.exe -log CPU9bits.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits.tcl -notrace
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# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/CPU9bits.vdi
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# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1\vivado.jou
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#-----------------------------------------------------------
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source CPU9bits.tcl -notrace
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Command: link_design -top CPU9bits -part xc7k160tifbg484-2L
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Design is defaulting to srcset: sources_1
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Design is defaulting to constrset: constrs_1
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INFO: [Project 1-479] Netlist was created with Vivado 2018.3
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INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
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INFO: [Project 1-570] Preparing netlist for logic optimization
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 583.273 ; gain = 0.000
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INFO: [Project 1-111] Unisim Transformation Summary:
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No Unisim elements were transformed.
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4 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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link_design completed successfully
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link_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 588.785 ; gain = 334.348
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Command: opt_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
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Running DRC as a precondition to command opt_design
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Starting DRC Task
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Project 1-461] DRC finished with 0 Errors
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INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.165 . Memory (MB): peak = 592.141 ; gain = 3.355
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Starting Cache Timing Information Task
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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Ending Cache Timing Information Task | Checksum: 16212f689
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Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1080.938 ; gain = 488.797
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Starting Logic Optimization Task
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Phase 1 Retarget
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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INFO: [Opt 31-49] Retargeted 0 cell(s).
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Phase 1 Retarget | Checksum: 16212f689
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1175.109 ; gain = 0.000
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INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
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Phase 2 Constant propagation
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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Phase 2 Constant propagation | Checksum: 16212f689
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1175.109 ; gain = 0.000
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INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
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Phase 3 Sweep
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Phase 3 Sweep | Checksum: 16212f689
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1175.109 ; gain = 0.000
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INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
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Phase 4 BUFG optimization
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Phase 4 BUFG optimization | Checksum: 16212f689
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1175.109 ; gain = 0.000
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INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
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Phase 5 Shift Register Optimization
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Phase 5 Shift Register Optimization | Checksum: 16212f689
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.087 . Memory (MB): peak = 1175.109 ; gain = 0.000
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INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
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Phase 6 Post Processing Netlist
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Phase 6 Post Processing Netlist | Checksum: 16212f689
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.087 . Memory (MB): peak = 1175.109 ; gain = 0.000
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INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
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Opt_design Change Summary
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=========================
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-------------------------------------------------------------------------------------------------------------------------
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| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
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-------------------------------------------------------------------------------------------------------------------------
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| Retarget | 0 | 0 | 0 |
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| Constant propagation | 0 | 0 | 0 |
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| Sweep | 0 | 0 | 0 |
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| BUFG optimization | 0 | 0 | 0 |
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| Shift Register Optimization | 0 | 0 | 0 |
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| Post Processing Netlist | 0 | 0 | 0 |
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-------------------------------------------------------------------------------------------------------------------------
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Starting Connectivity Check Task
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1175.109 ; gain = 0.000
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Ending Logic Optimization Task | Checksum: 16212f689
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.090 . Memory (MB): peak = 1175.109 ; gain = 0.000
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Starting Power Optimization Task
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INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
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Ending Power Optimization Task | Checksum: 16212f689
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1175.109 ; gain = 0.000
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Starting Final Cleanup Task
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Ending Final Cleanup Task | Checksum: 16212f689
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1175.109 ; gain = 0.000
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Starting Netlist Obfuscation Task
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1175.109 ; gain = 0.000
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Ending Netlist Obfuscation Task | Checksum: 16212f689
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1175.109 ; gain = 0.000
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INFO: [Common 17-83] Releasing license: Implementation
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20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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opt_design completed successfully
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opt_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1175.109 ; gain = 586.324
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1175.109 ; gain = 0.000
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WARNING: [Constraints 18-5210] No constraints selected for write.
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Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
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INFO: [Common 17-1381] The checkpoint 'C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/CPU9bits_opt.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx
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Command: report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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INFO: [IP_Flow 19-1704] No user IP repositories specified
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INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.3/data/ip'.
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/CPU9bits_drc_opted.rpt.
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report_drc completed successfully
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Command: place_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Running DRC as a precondition to command place_design
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Starting Placer Task
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INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
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Phase 1 Placer Initialization
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Phase 1.1 Placer Initialization Netlist Sorting
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1195.590 ; gain = 0.000
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Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 9761e0e0
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1195.590 ; gain = 0.000
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1195.590 ; gain = 0.000
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Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 19236f07e
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1204.129 ; gain = 8.539
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Phase 1.3 Build Placer Netlist Model
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Phase 1.3 Build Placer Netlist Model | Checksum: 1e494ed1a
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1204.129 ; gain = 8.539
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Phase 1.4 Constrain Clocks/Macros
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Phase 1.4 Constrain Clocks/Macros | Checksum: 1e494ed1a
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1204.129 ; gain = 8.539
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Phase 1 Placer Initialization | Checksum: 1e494ed1a
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1204.129 ; gain = 8.539
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Phase 2 Final Placement Cleanup
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1204.129 ; gain = 0.000
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Phase 2 Final Placement Cleanup | Checksum: 1e494ed1a
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1204.129 ; gain = 8.539
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INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed
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Ending Placer Task | Checksum: 19236f07e
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1204.129 ; gain = 8.539
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INFO: [Common 17-83] Releasing license: Implementation
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38 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
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place_design completed successfully
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1204.129 ; gain = 0.000
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WARNING: [Constraints 18-5210] No constraints selected for write.
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Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
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Writing placer database...
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Writing XDEF routing.
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Writing XDEF routing logical nets.
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Writing XDEF routing special nets.
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Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.122 . Memory (MB): peak = 1204.129 ; gain = 0.000
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INFO: [Common 17-1381] The checkpoint 'C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/CPU9bits_placed.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_io -file CPU9bits_io_placed.rpt
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report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.086 . Memory (MB): peak = 1210.254 ; gain = 6.125
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INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb
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INFO: [runtcl-4] Executing : report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt
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report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1210.254 ; gain = 0.000
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Command: route_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
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Running DRC as a precondition to command route_design
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Starting Routing Task
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INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
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Checksum: PlaceDB: fad50f9e ConstDB: 0 ShapeSum: 9761e0e0 RouteDB: 0
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Phase 1 Build RT Design
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Phase 1 Build RT Design | Checksum: ae2d8a92
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Time (s): cpu = 00:00:41 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.336 ; gain = 223.395
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Post Restoration Checksum: NetGraph: 87f14705 NumContArr: 263c438d Constraints: 0 Timing: 0
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Phase 2 Router Initialization
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INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
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Phase 2.1 Fix Topology Constraints
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Phase 2.1 Fix Topology Constraints | Checksum: ae2d8a92
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Time (s): cpu = 00:00:41 ; elapsed = 00:00:30 . Memory (MB): peak = 1440.074 ; gain = 227.133
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Phase 2.2 Pre Route Cleanup
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Phase 2.2 Pre Route Cleanup | Checksum: ae2d8a92
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Time (s): cpu = 00:00:41 ; elapsed = 00:00:30 . Memory (MB): peak = 1440.074 ; gain = 227.133
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Number of Nodes with overlaps = 0
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Phase 2 Router Initialization | Checksum: 6e1873f8
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Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1448.008 ; gain = 235.066
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Phase 3 Initial Routing
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Number of Nodes with overlaps = 0
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Phase 3 Initial Routing | Checksum: 6e1873f8
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Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1452.438 ; gain = 239.496
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Phase 4 Rip-up And Reroute
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Phase 4.1 Global Iteration 0
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Phase 4.1 Global Iteration 0 | Checksum: 6e1873f8
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Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1452.438 ; gain = 239.496
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Phase 4 Rip-up And Reroute | Checksum: 6e1873f8
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Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1452.438 ; gain = 239.496
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Phase 5 Delay and Skew Optimization
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Phase 5 Delay and Skew Optimization | Checksum: 6e1873f8
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Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1452.438 ; gain = 239.496
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Phase 6 Post Hold Fix
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Phase 6.1 Hold Fix Iter
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Phase 6.1 Hold Fix Iter | Checksum: 6e1873f8
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Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1452.438 ; gain = 239.496
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Phase 6 Post Hold Fix | Checksum: 6e1873f8
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Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1452.438 ; gain = 239.496
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Phase 7 Route finalize
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Router Utilization Summary
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Global Vertical Routing Utilization = 0 %
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Global Horizontal Routing Utilization = 0 %
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Routable Net Status*
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*Does not include unroutable nets such as driverless and loadless.
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Run report_route_status for detailed report.
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Number of Failed Nets = 0
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Number of Unrouted Nets = 0
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Number of Partially Routed Nets = 0
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Number of Node Overlaps = 0
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Congestion Report
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North Dir 1x1 Area, Max Cong = 0%, No Congested Regions.
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South Dir 1x1 Area, Max Cong = 0%, No Congested Regions.
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East Dir 1x1 Area, Max Cong = 0%, No Congested Regions.
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West Dir 1x1 Area, Max Cong = 0%, No Congested Regions.
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------------------------------
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Reporting congestion hotspots
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------------------------------
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Direction: North
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----------------
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Congested clusters found at Level 0
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Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
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Direction: South
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----------------
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Congested clusters found at Level 0
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Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
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Direction: East
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----------------
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Congested clusters found at Level 0
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Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
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Direction: West
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----------------
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Congested clusters found at Level 0
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Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
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Phase 7 Route finalize | Checksum: 6e1873f8
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Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1452.438 ; gain = 239.496
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Phase 8 Verifying routed nets
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Verification completed successfully
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Phase 8 Verifying routed nets | Checksum: 6e1873f8
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Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1454.441 ; gain = 241.500
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Phase 9 Depositing Routes
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Phase 9 Depositing Routes | Checksum: 6e1873f8
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Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1454.441 ; gain = 241.500
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INFO: [Route 35-16] Router Completed Successfully
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Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1454.441 ; gain = 241.500
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Routing Is Done.
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INFO: [Common 17-83] Releasing license: Implementation
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50 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
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route_design completed successfully
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route_design: Time (s): cpu = 00:00:43 ; elapsed = 00:00:32 . Memory (MB): peak = 1454.441 ; gain = 244.188
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1454.441 ; gain = 0.000
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WARNING: [Constraints 18-5210] No constraints selected for write.
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Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
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Writing placer database...
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Writing XDEF routing.
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Writing XDEF routing logical nets.
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Writing XDEF routing special nets.
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Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.050 . Memory (MB): peak = 1454.441 ; gain = 0.000
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INFO: [Common 17-1381] The checkpoint 'C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/CPU9bits_routed.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx
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Command: report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx
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INFO: [IP_Flow 19-1839] IP Catalog is up to date.
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/CPU9bits_drc_routed.rpt.
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report_drc completed successfully
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INFO: [runtcl-4] Executing : report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx
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Command: report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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INFO: [DRC 23-133] Running Methodology with 2 threads
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INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.rpt.
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report_methodology completed successfully
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INFO: [runtcl-4] Executing : report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx
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Command: report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx
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WARNING: [Power 33-232] No user defined clocks were found in the design!
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Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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Running Vector-less Activity Propagation...
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Finished Running Vector-less Activity Propagation
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61 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
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report_power completed successfully
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INFO: [runtcl-4] Executing : report_route_status -file CPU9bits_route_status.rpt -pb CPU9bits_route_status.pb
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INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation
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INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max.
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INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
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WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
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INFO: [runtcl-4] Executing : report_incremental_reuse -file CPU9bits_incremental_reuse_routed.rpt
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INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
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INFO: [runtcl-4] Executing : report_clock_utilization -file CPU9bits_clock_utilization_routed.rpt
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INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx
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INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max.
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INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
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INFO: [Common 17-206] Exiting Vivado at Wed Mar 13 11:13:49 2019...
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