William/WMU-ECE-3570-Lab
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WMU-ECE-3570-Lab/lab2CA.srcs/sources_1/new
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Johannes 033e606d5d Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
#	lab2CA.srcs/sources_1/new/dataMemory.v
#	lab2CA.srcs/sources_1/new/instructionMemory.v
#	lab2CA.xpr
2019-03-24 17:08:42 -04:00
..
ALU.v
Added zeroing instr
2019-03-16 14:34:36 -04:00
BasicModules.v
Added zeroing instr
2019-03-16 14:34:36 -04:00
ControlUnit.v
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
2019-03-24 16:06:29 -04:00
CPU9bits.v
String Compare Working
2019-03-24 17:05:09 -04:00
dataMemory.v
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
2019-03-24 17:08:42 -04:00
FetchUnit.v
Better Sim
2019-03-14 14:37:58 -04:00
instructionMemory.v
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
2019-03-24 17:08:42 -04:00
RegFile.v
Fixed bugs, finished BEQ, Added Halt
2019-03-13 11:14:52 -04:00