Go to file

Johannes 033e606d5d Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2

# Conflicts:
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
#	lab2CA.srcs/sources_1/new/dataMemory.v
#	lab2CA.srcs/sources_1/new/instructionMemory.v
#	lab2CA.xpr

2019-03-24 17:08:42 -04:00

lab2CA.cache/wt

String Compare Working

2019-03-24 17:05:09 -04:00

lab2CA.ip_user_files

fetch unit

2019-02-15 11:20:14 -05:00

lab2CA.runs

String Compare Working

2019-03-24 17:05:09 -04:00

lab2CA.sim/sim_1

Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2

2019-03-24 17:08:42 -04:00

lab2CA.srcs/sources_1

Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2

2019-03-24 17:08:42 -04:00

.gitignore

Excluded Markdown files

2019-02-21 15:11:10 -05:00

Bank_behav1.wcfg

Added Binary Search Code

2019-03-24 16:35:59 -04:00

CPU9bits_tb_behav.wcfg

BEQ and LD fix

2019-03-24 16:05:16 -04:00

lab2CA.xpr

String Compare Working

2019-03-24 17:05:09 -04:00

README.md

Updated README

2019-03-12 21:53:50 -04:00

regFile_tb_behav.wcfg

Better Sim

2019-03-14 14:37:58 -04:00

StringCompare.wcfg

String Compare Working

2019-03-24 17:05:09 -04:00

vivado_10872.backup.jou

stuff

2019-02-16 12:37:12 -05:00

vivado_15076.backup.jou

new thing

2019-02-16 13:04:06 -05:00

vivado_15356.backup.jou

more stuff

2019-02-16 12:42:09 -05:00

vivado.jou

new thing

2019-02-16 13:04:06 -05:00

README.md

ECE 3570 Lab

Unknown Status of Fixes

Only two registers are being written to, first two within simulation is not being written to