44 lines
735 B
Verilog
44 lines
735 B
Verilog
`timescale 1ns / 1ps
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module CPU9bits(input wire [8:0] instr,
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input wire reset, clk,
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output reg done
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);
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wire [8:0] op1, op2;
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RegFile RF(
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.clk(clk),
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.reset(reset),
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.enable(),
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.write_index(),
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.op0_idx(),
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.op1_idx(),
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.write_data(),
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.op0(op0),
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.op1(op1)
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);
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FetchUnit FU(
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.clk(clk),
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.reset(reset),
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.op_idx(),
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.AddrIn(),
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.AddrOut()
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);
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ALU alu(
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.opcode(),
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.operand0(op0),
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.operand1(op1),
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.result()
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);
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//Make control unit here
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//------------------------------
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endmodule
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