WilliamMiceli 365fb5f648 Moved ALU from simulation sources to design sources

2019-02-15 16:15:41 -05:00

..

ALU.v

Moved ALU from simulation sources to design sources

2019-02-15 16:15:41 -05:00

BasicModules.v

Added 1-bit NOR

2019-02-15 16:05:07 -05:00

fetchFile.v

fetch unit

2019-02-15 11:20:14 -05:00

FetchUnit.v

Modularized project; mux, clock, and reg done; Progress on RegFile

2019-02-15 12:24:26 -05:00

lab2testing.v

Modularized project; mux, clock, and reg done; Progress on RegFile

2019-02-15 12:24:26 -05:00

RegFile.v

Removed comment blocks

2019-02-15 14:34:59 -05:00