WilliamMiceli 365fb5f648 Moved ALU from simulation sources to design sources

2019-02-15 16:15:41 -05:00

lab2CA.cache/wt

Added 1-bit adder

2019-02-15 14:55:11 -05:00

lab2CA.ip_user_files

fetch unit

2019-02-15 11:20:14 -05:00

lab2CA.srcs/sources_1/new

Moved ALU from simulation sources to design sources

2019-02-15 16:15:41 -05:00

.gitignore

Initial commit, gitignore

2019-02-08 18:10:13 -05:00

lab2CA.xpr

Framework of ALU is pretty much done

2019-02-15 15:57:04 -05:00

vivado.jou

Forgot to stage this file

2019-02-15 11:53:54 -05:00

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5.2 MiB

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