WilliamMiceli 582c80998e Added 8:1 MUX

2019-02-15 17:02:11 -05:00

..

ALU.v

Fixed ALU to use the inputs we're actually going to be giving it

2019-02-15 16:19:42 -05:00

BasicModules.v

Added 8:1 MUX

2019-02-15 17:02:11 -05:00

fetchFile.v

fetch unit

2019-02-15 11:20:14 -05:00

FetchUnit.v

Modularized project; mux, clock, and reg done; Progress on RegFile

2019-02-15 12:24:26 -05:00

lab2testing.v

Modularized project; mux, clock, and reg done; Progress on RegFile

2019-02-15 12:24:26 -05:00

RegFile.v

Added outputs to the MUXes for the registers

2019-02-15 17:01:43 -05:00