426 lines
7.4 KiB
Verilog
426 lines
7.4 KiB
Verilog
`timescale 1ns / 1ps
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module adder_1bit(
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input wire A,
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input wire B,
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input wire Cin,
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output wire S,
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output wire Cout);
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assign S = (A ^ B) ^ Cin;
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assign Cout = ((A ^ B) & Cin) | (A & B);
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endmodule
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module adder_9bit(
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input wire [8:0] A,
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input wire [8:0] B,
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input wire Cin,
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output wire [8:0] Sum,
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output wire Cout);
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wire C_add0;
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wire C_add1;
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wire C_add2;
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wire C_add3;
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wire C_add4;
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wire C_add5;
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wire C_add6;
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wire C_add7;
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adder_1bit add0(
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.A(A[0]),
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.B(B[0]),
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.Cin(Cin),
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.S(Sum[0]),
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.Cout(C_add0));
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adder_1bit add1(
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.A(A[1]),
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.B(B[1]),
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.Cin(C_add0),
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.S(Sum[1]),
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.Cout(C_add1));
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adder_1bit add2(
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.A(A[2]),
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.B(B[2]),
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.Cin(C_add1),
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.S(Sum[2]),
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.Cout(C_add2));
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adder_1bit add3(
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.A(A[3]),
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.B(B[3]),
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.Cin(C_add2),
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.S(Sum[3]),
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.Cout(C_add3));
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adder_1bit add4(
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.A(A[4]),
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.B(B[4]),
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.Cin(C_add3),
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.S(Sum[4]),
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.Cout(C_add4));
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adder_1bit add5(
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.A(A[5]),
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.B(B[5]),
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.Cin(C_add4),
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.S(Sum[5]),
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.Cout(C_add5));
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adder_1bit add6(
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.A(A[6]),
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.B(B[6]),
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.Cin(C_add5),
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.S(Sum[6]),
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.Cout(C_add6));
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adder_1bit add7(
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.A(A[7]),
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.B(B[7]),
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.Cin(C_add6),
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.S(Sum[7]),
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.Cout(C_add7));
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adder_1bit add8(
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.A(A[8]),
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.B(B[8]),
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.Cin(C_add7),
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.S(Sum[8]),
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.Cout(Cout));
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endmodule
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module and_1bit(
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input wire A,
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input wire B,
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output wire C);
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assign C = A & B;
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endmodule
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module and_9bit(
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input wire [8:0] A,
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input wire [8:0] B,
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output wire [8:0] C);
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and_1bit and0(
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.A(A[0]),
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.B(B[0]),
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.C(C[0]));
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and_1bit and1(
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.A(A[1]),
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.B(B[1]),
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.C(C[1]));
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and_1bit and2(
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.A(A[2]),
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.B(B[2]),
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.C(C[2]));
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and_1bit and3(
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.A(A[3]),
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.B(B[3]),
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.C(C[3]));
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and_1bit and4(
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.A(A[4]),
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.B(B[4]),
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.C(C[4]));
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and_1bit and5(
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.A(A[5]),
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.B(B[5]),
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.C(C[5]));
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and_1bit and6(
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.A(A[6]),
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.B(B[6]),
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.C(C[6]));
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and_1bit and7(
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.A(A[7]),
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.B(B[7]),
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.C(C[7]));
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and_1bit and8(
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.A(A[8]),
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.B(B[8]),
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.C(C[8]));
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endmodule
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module gen_clock();
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reg clk;
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initial begin
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clk = 1'b0;
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end
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always begin
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#5 clk = ~clk; // Period to be determined
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end
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endmodule
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module mux_4_1(input wire [1:0] switch,
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input wire [8:0] A,B,C,D,
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output reg [8:0] out);
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always @(A,B,C,D,switch) begin
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case (switch)
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2'b00 : out = A;
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2'b01 : out = B;
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2'b10 : out = C;
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2'b11 : out = D;
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default : out = 9'bxxxxxxxxx;
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endcase
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end
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endmodule
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module mux_8_1(
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input wire [2:0] switch,
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input wire [8:0] A,B,C,D,E,F,G,H,
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output reg [8:0] out);
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always @(A,B,C,D,E,F,G,H,switch) begin
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case (switch)
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3'b000 : out = A;
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3'b001 : out = B;
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3'b010 : out = C;
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3'b011 : out = D;
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3'b100 : out = E;
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3'b101 : out = F;
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3'b110 : out = G;
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3'b111 : out = H;
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default : out = 9'bxxxxxxxxx;
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endcase
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end
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endmodule
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module mux_16_1(
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input wire [3:0] switch,
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input wire [8:0] A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P,
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output reg [8:0] out);
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always @(A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P,switch) begin
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case (switch)
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4'b0000 : out = A;
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4'b0001 : out = B;
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4'b0010 : out = C;
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4'b0011 : out = D;
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4'b0100 : out = E;
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4'b0101 : out = F;
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4'b0110 : out = G;
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4'b0111 : out = H;
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4'b1000 : out = I;
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4'b1001 : out = J;
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4'b1010 : out = K;
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4'b1011 : out = L;
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4'b1100 : out = M;
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4'b1101 : out = N;
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4'b1110 : out = O;
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4'b1111 : out = P;
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default : out = 9'bxxxxxxxxx;
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endcase
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end
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endmodule
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module nor_1bit(
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input wire A,
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input wire B,
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output wire C);
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assign C = A |~ B;
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endmodule
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module nor_9bit(
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input wire [8:0] A,
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input wire [8:0] B,
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output wire [8:0] C);
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nor_1bit nor0(
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.A(A[0]),
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.B(B[0]),
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.C(C[0]));
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nor_1bit nor1(
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.A(A[1]),
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.B(B[1]),
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.C(C[1]));
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nor_1bit nor2(
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.A(A[2]),
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.B(B[2]),
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.C(C[2]));
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nor_1bit nor3(
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.A(A[3]),
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.B(B[3]),
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.C(C[3]));
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nor_1bit nor4(
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.A(A[4]),
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.B(B[4]),
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.C(C[4]));
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nor_1bit nor5(
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.A(A[5]),
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.B(B[5]),
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.C(C[5]));
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nor_1bit nor6(
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.A(A[6]),
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.B(B[6]),
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.C(C[6]));
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nor_1bit nor7(
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.A(A[7]),
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.B(B[7]),
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.C(C[7]));
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nor_1bit nor8(
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.A(A[8]),
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.B(B[8]),
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.C(C[8]));
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endmodule
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module not_1bit(
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input wire A,
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output wire B);
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assign B = ~A;
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endmodule
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module not_9bit(
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input wire [8:0] A,
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output wire [8:0] B);
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not_1bit not0(
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.A(A[0]),
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.B(B[0]));
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not_1bit not1(
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.A(A[1]),
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.B(B[1]));
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not_1bit not2(
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.A(A[2]),
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.B(B[2]));
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not_1bit not3(
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.A(A[3]),
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.B(B[3]));
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not_1bit not4(
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.A(A[4]),
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.B(B[4]));
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not_1bit not5(
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.A(A[5]),
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.B(B[5]));
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not_1bit not6(
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.A(A[6]),
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.B(B[6]));
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not_1bit not7(
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.A(A[7]),
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.B(B[7]));
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not_1bit not8(
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.A(A[8]),
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.B(B[8]));
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endmodule
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module or_1bit(
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input wire A,
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input wire B,
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output wire C);
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assign C = A | B;
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endmodule
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module or_9bit(
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input wire [8:0] A,
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input wire [8:0] B,
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output wire [8:0] C);
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or_1bit or0(
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.A(A[0]),
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.B(B[0]),
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.C(C[0]));
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or_1bit or1(
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.A(A[1]),
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.B(B[1]),
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.C(C[1]));
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or_1bit or2(
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.A(A[2]),
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.B(B[2]),
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.C(C[2]));
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or_1bit or3(
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.A(A[3]),
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.B(B[3]),
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.C(C[3]));
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or_1bit or4(
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.A(A[4]),
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.B(B[4]),
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.C(C[4]));
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or_1bit or5(
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.A(A[5]),
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.B(B[5]),
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.C(C[5]));
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or_1bit or6(
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.A(A[6]),
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.B(B[6]),
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.C(C[6]));
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or_1bit or7(
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.A(A[7]),
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.B(B[7]),
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.C(C[7]));
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or_1bit or8(
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.A(A[8]),
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.B(B[8]),
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.C(C[8]));
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endmodule
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module register(input wire clk, reset,
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input wire [1:0] En,
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input wire [8:0] Din,
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output reg [8:0] Dout);
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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Dout <= 9'b000000000;
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end
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else if (En == 2'b00) begin
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Dout <= Din;
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end
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else begin
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Dout <= "ZZZZZZZZZ";
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end
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end
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endmodule |