9 lines
249 B
Plaintext
9 lines
249 B
Plaintext
# compile verilog/system verilog design source files
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verilog xil_defaultlib \
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"alu_tb_func_impl.v" \
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"../../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \
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"../../../../../lab2CA.srcs/sources_1/new/ALU.v" \
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# Do not sort compile order
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nosort
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