William/WMU-ECE-3570-Lab

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WilliamMiceli 5bd244f9ba Now Asynchronous and recognized by Vivado as RTL_ROM

2019-03-29 16:13:07 -04:00

lab2CA.cache/wt

Added test data for programs to run

2019-03-25 16:00:32 -04:00

lab2CA.ip_user_files

fetch unit

2019-02-15 11:20:14 -05:00

Making fixes to Bubble Sort

2019-03-24 19:27:59 -04:00

lab2CA.sim/sim_1

Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2

2019-03-24 19:31:28 -04:00

lab2CA.srcs/sources_1

Now Asynchronous and recognized by Vivado as RTL_ROM

2019-03-29 16:13:07 -04:00

.gitignore

Excluded Markdown files

2019-02-21 15:11:10 -05:00

Bank_behav1.wcfg

Binary Search completed

2019-03-24 17:30:27 -04:00

CPU9bits_tb_behav.wcfg

Making fixes to Bubble Sort

2019-03-24 19:27:59 -04:00

lab2CA.xpr

Making fixes to Bubble Sort

2019-03-24 19:27:59 -04:00

README.md

Aded list of things to fix

2019-03-25 18:04:44 -04:00

regFile_tb_behav.wcfg

Better Sim

2019-03-14 14:37:58 -04:00

StringCompare.wcfg

String Compare Working

2019-03-24 17:05:09 -04:00

vivado_10872.backup.jou

stuff

2019-02-16 12:37:12 -05:00

vivado_15076.backup.jou

new thing

2019-02-16 13:04:06 -05:00

vivado_15356.backup.jou

more stuff

2019-02-16 12:42:09 -05:00

vivado.jou

new thing

2019-02-16 13:04:06 -05:00

README.md

ECE 3570 Lab

Things to fix

Make RAM write edge-triggered only
- RTL_RAM is what it needs to be showing as, since VIvado will recognize it as such
Make ROM asyncronous (can be read at any time)
- RTL_ROM is what it needs to be showing as, since VIvado will recognize it as such
Get rid of if statememnts in RAM and ROM
Get programs working properly