 WilliamMiceli
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5bd244f9ba
|
Now Asynchronous and recognized by Vivado as RTL_ROM
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2019-03-29 16:13:07 -04:00 |
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WilliamMiceli
|
5c165d603a
|
Added drivers for unused operations in MUX, so Vivado doesn't show the warning of being undriven
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2019-03-29 16:11:52 -04:00 |
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WilliamMiceli
|
03eb3f3740
|
Commented out Program 1 test
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2019-03-29 14:57:29 -04:00 |
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WilliamMiceli
|
ce86652a00
|
Aded list of things to fix
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2019-03-25 18:04:44 -04:00 |
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|
WilliamMiceli
|
97fcfb7ef1
|
Fixed equation solver instructions
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2019-03-25 17:08:22 -04:00 |
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WilliamMiceli
|
2420d52fc3
|
Added test data for programs to run
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2019-03-25 16:00:32 -04:00 |
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WilliamMiceli
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5353c8c22e
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Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
# Conflicts:
# lab2CA.cache/wt/webtalk_pa.xml
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
# lab2CA.srcs/sources_1/new/CPU9bits.v
# lab2CA.srcs/sources_1/new/dataMemory.v
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2019-03-24 19:31:28 -04:00 |
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WilliamMiceli
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7490815502
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Making fixes to Bubble Sort
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2019-03-24 19:27:59 -04:00 |
|
 Johannes
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65b951cf82
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Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
# Conflicts:
# Bank_behav1.wcfg
# lab2CA.runs/.jobs/vrs_config_42.xml
# lab2CA.runs/impl_1/CPU9bits_tb.tcl
# lab2CA.runs/impl_1/gen_run.xml
# lab2CA.runs/impl_1/htr.txt
# lab2CA.runs/impl_1/init_design.pb
# lab2CA.runs/impl_1/opt_design.pb
# lab2CA.runs/impl_1/place_design.pb
# lab2CA.runs/impl_1/vivado.jou
# lab2CA.runs/impl_1/vivado.pb
# lab2CA.runs/synth_1/CPU9bits.dcp
# lab2CA.runs/synth_1/CPU9bits.vds
# lab2CA.runs/synth_1/CPU9bits_tb.tcl
# lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.rpt
# lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb
# lab2CA.runs/synth_1/gen_run.xml
# lab2CA.runs/synth_1/vivado.jou
# lab2CA.runs/synth_1/vivado.pb
# lab2CA.sim/sim_1/behav/xsim/webtalk.jou
# lab2CA.sim/sim_1/behav/xsim/webtalk_12056.backup.jou
# lab2CA.sim/sim_1/behav/xsim/webtalk_15032.backup.jou
# lab2CA.sim/sim_1/behav/xsim/xelab.pb
# lab2CA.sim/sim_1/behav/xsim/xvlog.pb
# lab2CA.srcs/sources_1/new/instructionMemory.v
# lab2CA.xpr
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2019-03-24 19:02:52 -04:00 |
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Johannes
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be06f4e457
|
Just changes made for simulations
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2019-03-24 18:55:49 -04:00 |
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WilliamMiceli
|
4354aebf8c
|
Merged files
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2019-03-24 17:43:32 -04:00 |
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WilliamMiceli
|
681c506eec
|
Renamed signals on simulation waveforms
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2019-03-24 17:42:38 -04:00 |
|
 jose.rodriguezlabra
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5a506ba3ab
|
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
# Conflicts:
# lab2CA.cache/wt/webtalk_pa.xml
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
# lab2CA.srcs/sources_1/new/instructionMemory.v
# lab2CA.xpr
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2019-03-24 17:33:42 -04:00 |
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jose.rodriguezlabra
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efbd7b773b
|
Binary Search completed
It is not fully tested, but it looks pretty good
|
2019-03-24 17:30:27 -04:00 |
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WilliamMiceli
|
1c44d8d964
|
Added comments to insructions
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2019-03-24 17:26:44 -04:00 |
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|
Johannes
|
033e606d5d
|
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
# Conflicts:
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
# lab2CA.srcs/sources_1/new/dataMemory.v
# lab2CA.srcs/sources_1/new/instructionMemory.v
# lab2CA.xpr
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2019-03-24 17:08:42 -04:00 |
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Johannes
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03df69372a
|
String Compare Working
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2019-03-24 17:05:09 -04:00 |
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WilliamMiceli
|
8e72409386
|
Added Bubble Sort instructions and initial data memory
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2019-03-24 16:54:06 -04:00 |
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jose.rodriguezlabra
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335280ccd5
|
Added Binary Search Code
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2019-03-24 16:35:59 -04:00 |
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WilliamMiceli
|
a978e1fbc6
|
Revert file
|
2019-03-24 16:11:31 -04:00 |
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Johannes
|
9a2e84bda6
|
metadata
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2019-03-24 16:09:40 -04:00 |
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Johannes
|
ace0eca65a
|
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
# Conflicts:
# lab2CA.xpr
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2019-03-24 16:06:29 -04:00 |
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jose.rodriguezlabra
|
eac5d71dd6
|
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
# Conflicts:
# lab2CA.cache/wt/webtalk_pa.xml
|
2019-03-24 16:05:40 -04:00 |
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Johannes
|
e8ada91e08
|
BEQ and LD fix
|
2019-03-24 16:05:16 -04:00 |
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jose.rodriguezlabra
|
ce2410e26c
|
little things
|
2019-03-24 16:04:55 -04:00 |
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WilliamMiceli
|
f17a0c8954
|
Replaced missing simulation configuration file
|
2019-03-24 15:52:26 -04:00 |
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|
jose.rodriguezlabra
|
27f6d24b88
|
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
# Conflicts:
# lab2CA.cache/wt/webtalk_pa.xml
# lab2CA.runs/impl_1/gen_run.xml
# lab2CA.runs/synth_1/gen_run.xml
# lab2CA.sim/sim_1/behav/xsim/xelab.pb
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
# lab2CA.sim/sim_1/behav/xsim/xvlog.pb
# lab2CA.srcs/sources_1/new/instructionMemory.v
# lab2CA.xpr
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2019-03-24 14:17:59 -04:00 |
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jose.rodriguezlabra
|
94f0267a13
|
stuff
|
2019-03-24 14:16:03 -04:00 |
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Johannes
|
ee9e420365
|
Added string compare to instruction and data memory
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2019-03-24 14:14:28 -04:00 |
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Johannes
|
395a8b6f8f
|
Revert "metadata"
This reverts commit 191ca46f2d.
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2019-03-24 13:01:08 -04:00 |
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Johannes
|
2af68f2731
|
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
|
2019-03-24 12:59:29 -04:00 |
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Johannes
|
a57af01a47
|
Revert "Changed datamemory"
This reverts commit 90d9d69885.
|
2019-03-24 12:49:08 -04:00 |
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Johannes
|
90d9d69885
|
Changed datamemory
|
2019-03-24 12:47:18 -04:00 |
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jose.rodriguezlabra
|
bab680ea27
|
Added bank to CPU9bits
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2019-03-24 12:11:12 -04:00 |
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jose.rodriguezlabra
|
191ca46f2d
|
metadata
|
2019-03-24 10:07:28 -04:00 |
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WilliamMiceli
|
ad6765a43a
|
BEQ Opcode fix & other stuffz
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2019-03-22 19:54:06 -04:00 |
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Johannes
|
c85ad153dc
|
Tested the instructions using the instruction memory
All of the instructions seem to be working other than beq. I might just be calling it wrong
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2019-03-20 12:08:24 -04:00 |
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Johannes
|
0f55e62a2e
|
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
|
2019-03-16 14:56:00 -04:00 |
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Johannes
|
e8554a5a9a
|
Minor changes to CPU
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2019-03-16 14:55:37 -04:00 |
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jose.rodriguezlabra
|
eeb9c7c318
|
Tested zero
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2019-03-16 14:55:11 -04:00 |
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Johannes
|
fa5caec5dd
|
Added memories to the CPU
|
2019-03-16 14:37:46 -04:00 |
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jose.rodriguezlabra
|
3c8147641f
|
Added zeroing instr
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2019-03-16 14:34:36 -04:00 |
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Johannes
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21e846ab62
|
Instruction & Data Memory
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2019-03-16 14:16:02 -04:00 |
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jose.rodriguezlabra
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dfd8753a62
|
Implemented SEs
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2019-03-16 14:09:53 -04:00 |
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jose.rodriguezlabra
|
5cbe490aae
|
Added link instruction
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2019-03-16 14:01:32 -04:00 |
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WilliamMiceli
|
934c73e899
|
Small formatting change
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2019-03-16 13:44:44 -04:00 |
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WilliamMiceli
|
b621f5a46b
|
Added sign extension for 3 bits up to 8 bits
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2019-03-16 13:23:22 -04:00 |
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WilliamMiceli
|
ef8b9c92e5
|
Made testbench
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2019-03-16 13:02:29 -04:00 |
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WilliamMiceli
|
c988ddb899
|
Fixed 2 bit module
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2019-03-16 13:02:18 -04:00 |
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WilliamMiceli
|
19ac8e130c
|
Added sign extension for 2 bits into 9 bits, just to test first
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2019-03-16 12:55:57 -04:00 |
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