Instruction & Data Memory
This commit is contained in:
Johannes
11
lab2CA.sim/sim_1/behav/xsim/dataMemory_tb.tcl
Normal file
11
lab2CA.sim/sim_1/behav/xsim/dataMemory_tb.tcl
Normal file
@@ -0,0 +1,11 @@
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set curr_wave [current_wave_config]
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if { [string length $curr_wave] == 0 } {
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if { [llength [get_objects]] > 0} {
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add_wave /
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set_property needs_save false [current_wave_config]
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} else {
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send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
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}
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}
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run 1000ns
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9
lab2CA.sim/sim_1/behav/xsim/dataMemory_tb_vlog.prj
Normal file
9
lab2CA.sim/sim_1/behav/xsim/dataMemory_tb_vlog.prj
Normal file
@@ -0,0 +1,9 @@
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# compile verilog/system verilog design source files
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verilog xil_defaultlib \
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"../../../../lab2CA.srcs/sources_1/new/dataMemory.v" \
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# compile glbl module
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verilog xil_defaultlib "glbl.v"
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# Do not sort compile order
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nosort
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11
lab2CA.sim/sim_1/behav/xsim/instructionMemory_tb.tcl
Normal file
11
lab2CA.sim/sim_1/behav/xsim/instructionMemory_tb.tcl
Normal file
@@ -0,0 +1,11 @@
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set curr_wave [current_wave_config]
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if { [string length $curr_wave] == 0 } {
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if { [llength [get_objects]] > 0} {
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add_wave /
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set_property needs_save false [current_wave_config]
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} else {
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send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
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}
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}
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run 1000ns
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@@ -0,0 +1,9 @@
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# compile verilog/system verilog design source files
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verilog xil_defaultlib \
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"../../../../lab2CA.srcs/sources_1/new/instructionMemory.v" \
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# compile glbl module
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verilog xil_defaultlib "glbl.v"
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# Do not sort compile order
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nosort
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@@ -1,12 +0,0 @@
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#-----------------------------------------------------------
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# Webtalk v2018.3 (64-bit)
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# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
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# Start of session at: Wed Mar 13 11:21:51 2019
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# Process ID: 11840
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# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim
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# Command line: wbtcv.exe -mode batch -source C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace
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# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
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# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
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#-----------------------------------------------------------
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source C:/Users/JoseIgnacio/CA -notrace
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12
lab2CA.sim/sim_1/behav/xsim/webtalk_13852.backup.jou
Normal file
12
lab2CA.sim/sim_1/behav/xsim/webtalk_13852.backup.jou
Normal file
@@ -0,0 +1,12 @@
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#-----------------------------------------------------------
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# Webtalk v2018.3 (64-bit)
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# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
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# Start of session at: Sat Mar 16 14:03:44 2019
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# Process ID: 13852
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# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
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# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace
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# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
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# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
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#-----------------------------------------------------------
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source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace
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12
lab2CA.sim/sim_1/behav/xsim/webtalk_14548.backup.jou
Normal file
12
lab2CA.sim/sim_1/behav/xsim/webtalk_14548.backup.jou
Normal file
@@ -0,0 +1,12 @@
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#-----------------------------------------------------------
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# Webtalk v2018.3 (64-bit)
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# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
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# Start of session at: Sat Mar 16 13:13:49 2019
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# Process ID: 14548
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# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
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# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace
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# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
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# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
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#-----------------------------------------------------------
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source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace
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@@ -1,12 +0,0 @@
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#-----------------------------------------------------------
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# Webtalk v2018.3 (64-bit)
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# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
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# Start of session at: Thu Mar 14 14:24:20 2019
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# Process ID: 14664
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# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim
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# Command line: wbtcv.exe -mode batch -source C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace
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# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
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# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
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#-----------------------------------------------------------
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source C:/Users/JoseIgnacio/CA -notrace
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@@ -1,12 +0,0 @@
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#-----------------------------------------------------------
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# Webtalk v2018.3 (64-bit)
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# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
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# Start of session at: Thu Mar 14 14:23:56 2019
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# Process ID: 17516
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# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim
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# Command line: wbtcv.exe -mode batch -source C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace
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# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
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# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
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#-----------------------------------------------------------
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source C:/Users/JoseIgnacio/CA -notrace
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12
lab2CA.sim/sim_1/behav/xsim/webtalk_7732.backup.jou
Normal file
12
lab2CA.sim/sim_1/behav/xsim/webtalk_7732.backup.jou
Normal file
@@ -0,0 +1,12 @@
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#-----------------------------------------------------------
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# Webtalk v2018.3 (64-bit)
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# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
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# Start of session at: Sat Mar 16 13:12:04 2019
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# Process ID: 7732
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# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
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# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace
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# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
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# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
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#-----------------------------------------------------------
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source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace
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Binary file not shown.
@@ -0,0 +1 @@
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-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" -L "xpm" --snapshot "dataMemory_tb_behav" "xil_defaultlib.dataMemory_tb" "xil_defaultlib.glbl" -log "elaborate.log"
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@@ -0,0 +1 @@
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Breakpoint File Version 1.0
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@@ -0,0 +1,113 @@
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/**********************************************************************/
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/* ____ ____ */
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/* / /\/ / */
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/* /___/ \ / */
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/* \ \ \/ */
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/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
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/* / / All Right Reserved. */
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/* /---/ /\ */
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/* \ \ / \ */
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/* \___\/\___\ */
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/**********************************************************************/
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#include "iki.h"
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#include <string.h>
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#include <math.h>
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#ifdef __GNUC__
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#include <stdlib.h>
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#else
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#include <malloc.h>
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#define alloca _alloca
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#endif
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/**********************************************************************/
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/* ____ ____ */
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/* / /\/ / */
|
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/* /___/ \ / */
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/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
|
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/* / / All Right Reserved. */
|
||||
/* /---/ /\ */
|
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/* \ \ / \ */
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/* \___\/\___\ */
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/**********************************************************************/
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#include "iki.h"
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#include <string.h>
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#include <math.h>
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#ifdef __GNUC__
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#include <stdlib.h>
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#else
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#include <malloc.h>
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#define alloca _alloca
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#endif
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typedef void (*funcp)(char *, char *);
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extern int main(int, char**);
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extern void execute_2(char*, char *);
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extern void execute_3(char*, char *);
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extern void execute_7(char*, char *);
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extern void execute_12(char*, char *);
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extern void execute_13(char*, char *);
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extern void execute_14(char*, char *);
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extern void execute_15(char*, char *);
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extern void execute_16(char*, char *);
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extern void execute_5(char*, char *);
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extern void execute_6(char*, char *);
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extern void execute_9(char*, char *);
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extern void execute_10(char*, char *);
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extern void execute_11(char*, char *);
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extern void execute_17(char*, char *);
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extern void execute_18(char*, char *);
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extern void execute_19(char*, char *);
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extern void execute_20(char*, char *);
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extern void execute_21(char*, char *);
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extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
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funcp funcTab[19] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_7, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_5, (funcp)execute_6, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_17, (funcp)execute_18, (funcp)execute_19, (funcp)execute_20, (funcp)execute_21, (funcp)vlog_transfunc_eventcallback};
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const int NumRelocateId= 19;
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void relocate(char *dp)
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{
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iki_relocate(dp, "xsim.dir/dataMemory_tb_behav/xsim.reloc", (void **)funcTab, 19);
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||||
|
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/*Populate the transaction function pointer field in the whole net structure */
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||||
}
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||||
|
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void sensitize(char *dp)
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{
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iki_sensitize(dp, "xsim.dir/dataMemory_tb_behav/xsim.reloc");
|
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}
|
||||
|
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void simulate(char *dp)
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{
|
||||
iki_schedule_processes_at_time_zero(dp, "xsim.dir/dataMemory_tb_behav/xsim.reloc");
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||||
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
|
||||
iki_execute_processes();
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||||
|
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// Schedule resolution functions for the multiply driven Verilog nets that have strength
|
||||
// Schedule transaction functions for the singly driven Verilog nets that have strength
|
||||
|
||||
}
|
||||
#include "iki_bridge.h"
|
||||
void relocate(char *);
|
||||
|
||||
void sensitize(char *);
|
||||
|
||||
void simulate(char *);
|
||||
|
||||
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
|
||||
extern void implicit_HDL_SCinstatiate();
|
||||
|
||||
extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
|
||||
extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
|
||||
iki_set_sv_type_file_path_name("xsim.dir/dataMemory_tb_behav/xsim.svtype");
|
||||
iki_set_crvs_dump_file_path_name("xsim.dir/dataMemory_tb_behav/xsim.crvsdump");
|
||||
void* design_handle = iki_create_design("xsim.dir/dataMemory_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv);
|
||||
iki_set_rc_trial_count(100);
|
||||
(void) design_handle;
|
||||
return iki_simulate_design();
|
||||
}
|
||||
@@ -0,0 +1,44 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<webTalkData fileName='usage_statistics_ext_xsim.xml' majorVersion='1' minorVersion='0' timeStamp='Sat Mar 16 14:04:40 2019'>
|
||||
<section name="__ROOT__" level="0" order="1" description="">
|
||||
<section name="software_version_and_target_device" level="1" order="1" description="">
|
||||
<keyValuePair key="beta" value="FALSE" description="" />
|
||||
<keyValuePair key="build_version" value="2405991" description="" />
|
||||
<keyValuePair key="date_generated" value="Sat Mar 16 14:04:39 2019" description="" />
|
||||
<keyValuePair key="os_platform" value="WIN64" description="" />
|
||||
<keyValuePair key="product_version" value="XSIM v2018.3 (64-bit)" description="" />
|
||||
<keyValuePair key="project_id" value="0a5803efda44405bb28bbf43ba22e808" description="" />
|
||||
<keyValuePair key="project_iteration" value="2" description="" />
|
||||
<keyValuePair key="random_id" value="4e917e26-7591-4435-9135-15bd446b0238" description="" />
|
||||
<keyValuePair key="registration_id" value="174150793_174150794_210688225_140" description="" />
|
||||
<keyValuePair key="route_design" value="FALSE" description="" />
|
||||
<keyValuePair key="target_device" value="not_applicable" description="" />
|
||||
<keyValuePair key="target_family" value="not_applicable" description="" />
|
||||
<keyValuePair key="target_package" value="not_applicable" description="" />
|
||||
<keyValuePair key="target_speed" value="not_applicable" description="" />
|
||||
<keyValuePair key="tool_flow" value="xsim_vivado" description="" />
|
||||
</section>
|
||||
<section name="user_environment" level="1" order="2" description="">
|
||||
<keyValuePair key="cpu_name" value="Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" description="" />
|
||||
<keyValuePair key="cpu_speed" value="3492 MHz" description="" />
|
||||
<keyValuePair key="os_name" value="Microsoft Windows 8 or later , 64-bit" description="" />
|
||||
<keyValuePair key="os_release" value="major release (build 9200)" description="" />
|
||||
<keyValuePair key="system_ram" value="34.000 GB" description="" />
|
||||
<keyValuePair key="total_processors" value="1" description="" />
|
||||
</section>
|
||||
<section name="vivado_usage" level="1" order="3" description="">
|
||||
</section>
|
||||
<section name="xsim" level="1" order="4" description="">
|
||||
<section name="command_line_options" level="2" order="1" description="">
|
||||
<keyValuePair key="command" value="xsim" description="" />
|
||||
</section>
|
||||
<section name="usage" level="2" order="2" description="">
|
||||
<keyValuePair key="iteration" value="0" description="" />
|
||||
<keyValuePair key="runtime" value="40 ns" description="" />
|
||||
<keyValuePair key="simulation_memory" value="6668_KB" description="" />
|
||||
<keyValuePair key="simulation_time" value="0.05_sec" description="" />
|
||||
<keyValuePair key="trace_waveform" value="true" description="" />
|
||||
</section>
|
||||
</section>
|
||||
</section>
|
||||
</webTalkData>
|
||||
@@ -0,0 +1,42 @@
|
||||
webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/
|
||||
webtalk_register_client -client project
|
||||
webtalk_add_data -client project -key date_generated -value "Sat Mar 16 14:13:55 2019" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key registration_id -value "174150793_174150794_210688225_140" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key project_iteration -value "18" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
|
||||
webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment"
|
||||
webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment"
|
||||
webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user_environment"
|
||||
webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
|
||||
webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment"
|
||||
webtalk_register_client -client xsim
|
||||
webtalk_add_data -client xsim -key File_Counter -value "2" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key Simulation_Image_Code -value "69 KB" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Simulation_Image_Data -value "3 KB" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Total_Processes -value "24" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Total_Instances -value "3" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip unimacro_ver unisims_ver " -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Compiler_Time -value "0.73_sec" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Compiler_Memory -value "38176_KB" -context "xsim\\usage"
|
||||
webtalk_transmit -clientid 198226099 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
|
||||
webtalk_terminate
|
||||
Binary file not shown.
@@ -0,0 +1 @@
|
||||
-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" -L "xpm" --snapshot "instructionMemory_tb_behav" "xil_defaultlib.instructionMemory_tb" "xil_defaultlib.glbl" -log "elaborate.log"
|
||||
@@ -0,0 +1 @@
|
||||
Breakpoint File Version 1.0
|
||||
@@ -0,0 +1,111 @@
|
||||
/**********************************************************************/
|
||||
/* ____ ____ */
|
||||
/* / /\/ / */
|
||||
/* /___/ \ / */
|
||||
/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
|
||||
/* / / All Right Reserved. */
|
||||
/* /---/ /\ */
|
||||
/* \ \ / \ */
|
||||
/* \___\/\___\ */
|
||||
/**********************************************************************/
|
||||
|
||||
|
||||
#include "iki.h"
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
#ifdef __GNUC__
|
||||
#include <stdlib.h>
|
||||
#else
|
||||
#include <malloc.h>
|
||||
#define alloca _alloca
|
||||
#endif
|
||||
/**********************************************************************/
|
||||
/* ____ ____ */
|
||||
/* / /\/ / */
|
||||
/* /___/ \ / */
|
||||
/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
|
||||
/* / / All Right Reserved. */
|
||||
/* /---/ /\ */
|
||||
/* \ \ / \ */
|
||||
/* \___\/\___\ */
|
||||
/**********************************************************************/
|
||||
|
||||
|
||||
#include "iki.h"
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
#ifdef __GNUC__
|
||||
#include <stdlib.h>
|
||||
#else
|
||||
#include <malloc.h>
|
||||
#define alloca _alloca
|
||||
#endif
|
||||
typedef void (*funcp)(char *, char *);
|
||||
extern int main(int, char**);
|
||||
extern void execute_2(char*, char *);
|
||||
extern void execute_3(char*, char *);
|
||||
extern void execute_7(char*, char *);
|
||||
extern void execute_12(char*, char *);
|
||||
extern void execute_13(char*, char *);
|
||||
extern void execute_14(char*, char *);
|
||||
extern void execute_5(char*, char *);
|
||||
extern void execute_6(char*, char *);
|
||||
extern void execute_9(char*, char *);
|
||||
extern void execute_10(char*, char *);
|
||||
extern void execute_11(char*, char *);
|
||||
extern void execute_15(char*, char *);
|
||||
extern void execute_16(char*, char *);
|
||||
extern void execute_17(char*, char *);
|
||||
extern void execute_18(char*, char *);
|
||||
extern void execute_19(char*, char *);
|
||||
extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
|
||||
funcp funcTab[17] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_7, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_5, (funcp)execute_6, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)execute_19, (funcp)vlog_transfunc_eventcallback};
|
||||
const int NumRelocateId= 17;
|
||||
|
||||
void relocate(char *dp)
|
||||
{
|
||||
iki_relocate(dp, "xsim.dir/instructionMemory_tb_behav/xsim.reloc", (void **)funcTab, 17);
|
||||
|
||||
/*Populate the transaction function pointer field in the whole net structure */
|
||||
}
|
||||
|
||||
void sensitize(char *dp)
|
||||
{
|
||||
iki_sensitize(dp, "xsim.dir/instructionMemory_tb_behav/xsim.reloc");
|
||||
}
|
||||
|
||||
void simulate(char *dp)
|
||||
{
|
||||
iki_schedule_processes_at_time_zero(dp, "xsim.dir/instructionMemory_tb_behav/xsim.reloc");
|
||||
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
|
||||
iki_execute_processes();
|
||||
|
||||
// Schedule resolution functions for the multiply driven Verilog nets that have strength
|
||||
// Schedule transaction functions for the singly driven Verilog nets that have strength
|
||||
|
||||
}
|
||||
#include "iki_bridge.h"
|
||||
void relocate(char *);
|
||||
|
||||
void sensitize(char *);
|
||||
|
||||
void simulate(char *);
|
||||
|
||||
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
|
||||
extern void implicit_HDL_SCinstatiate();
|
||||
|
||||
extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
|
||||
extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
|
||||
iki_set_sv_type_file_path_name("xsim.dir/instructionMemory_tb_behav/xsim.svtype");
|
||||
iki_set_crvs_dump_file_path_name("xsim.dir/instructionMemory_tb_behav/xsim.crvsdump");
|
||||
void* design_handle = iki_create_design("xsim.dir/instructionMemory_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv);
|
||||
iki_set_rc_trial_count(100);
|
||||
(void) design_handle;
|
||||
return iki_simulate_design();
|
||||
}
|
||||
@@ -0,0 +1,44 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<webTalkData fileName='usage_statistics_ext_xsim.xml' majorVersion='1' minorVersion='0' timeStamp='Sat Mar 16 13:13:49 2019'>
|
||||
<section name="__ROOT__" level="0" order="1" description="">
|
||||
<section name="software_version_and_target_device" level="1" order="1" description="">
|
||||
<keyValuePair key="beta" value="FALSE" description="" />
|
||||
<keyValuePair key="build_version" value="2405991" description="" />
|
||||
<keyValuePair key="date_generated" value="Sat Mar 16 13:13:48 2019" description="" />
|
||||
<keyValuePair key="os_platform" value="WIN64" description="" />
|
||||
<keyValuePair key="product_version" value="XSIM v2018.3 (64-bit)" description="" />
|
||||
<keyValuePair key="project_id" value="0a5803efda44405bb28bbf43ba22e808" description="" />
|
||||
<keyValuePair key="project_iteration" value="2" description="" />
|
||||
<keyValuePair key="random_id" value="4e917e26-7591-4435-9135-15bd446b0238" description="" />
|
||||
<keyValuePair key="registration_id" value="174150793_174150794_210688225_140" description="" />
|
||||
<keyValuePair key="route_design" value="FALSE" description="" />
|
||||
<keyValuePair key="target_device" value="not_applicable" description="" />
|
||||
<keyValuePair key="target_family" value="not_applicable" description="" />
|
||||
<keyValuePair key="target_package" value="not_applicable" description="" />
|
||||
<keyValuePair key="target_speed" value="not_applicable" description="" />
|
||||
<keyValuePair key="tool_flow" value="xsim_vivado" description="" />
|
||||
</section>
|
||||
<section name="user_environment" level="1" order="2" description="">
|
||||
<keyValuePair key="cpu_name" value="Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" description="" />
|
||||
<keyValuePair key="cpu_speed" value="3492 MHz" description="" />
|
||||
<keyValuePair key="os_name" value="Microsoft Windows 8 or later , 64-bit" description="" />
|
||||
<keyValuePair key="os_release" value="major release (build 9200)" description="" />
|
||||
<keyValuePair key="system_ram" value="34.000 GB" description="" />
|
||||
<keyValuePair key="total_processors" value="1" description="" />
|
||||
</section>
|
||||
<section name="vivado_usage" level="1" order="3" description="">
|
||||
</section>
|
||||
<section name="xsim" level="1" order="4" description="">
|
||||
<section name="command_line_options" level="2" order="1" description="">
|
||||
<keyValuePair key="command" value="xsim" description="" />
|
||||
</section>
|
||||
<section name="usage" level="2" order="2" description="">
|
||||
<keyValuePair key="iteration" value="0" description="" />
|
||||
<keyValuePair key="runtime" value="30 ns" description="" />
|
||||
<keyValuePair key="simulation_memory" value="6648_KB" description="" />
|
||||
<keyValuePair key="simulation_time" value="0.05_sec" description="" />
|
||||
<keyValuePair key="trace_waveform" value="true" description="" />
|
||||
</section>
|
||||
</section>
|
||||
</section>
|
||||
</webTalkData>
|
||||
@@ -0,0 +1,32 @@
|
||||
webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/
|
||||
webtalk_register_client -client project
|
||||
webtalk_add_data -client project -key date_generated -value "Sat Mar 16 13:18:24 2019" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key registration_id -value "174150793_174150794_210688225_140" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key project_iteration -value "4" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
|
||||
webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment"
|
||||
webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment"
|
||||
webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user_environment"
|
||||
webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
|
||||
webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment"
|
||||
webtalk_register_client -client xsim
|
||||
webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key runtime -value "40 ns" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Simulation_Time -value "0.06_sec" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Simulation_Memory -value "6108_KB" -context "xsim\\usage"
|
||||
webtalk_transmit -clientid 3866550317 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
|
||||
webtalk_terminate
|
||||
Binary file not shown.
Binary file not shown.
89
lab2CA.srcs/sources_1/new/dataMemory.v
Normal file
89
lab2CA.srcs/sources_1/new/dataMemory.v
Normal file
@@ -0,0 +1,89 @@
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module dataMemory(
|
||||
input wire clk, writeEnable,
|
||||
input wire [8:0] address, writeData,
|
||||
output reg [8:0] readData
|
||||
);
|
||||
|
||||
reg [8:0] memory [15:0];
|
||||
|
||||
initial begin
|
||||
memory[0] <= 9'b000000000;
|
||||
memory[1] <= 9'b000000000;
|
||||
memory[2] <= 9'b000000000;
|
||||
memory[3] <= 9'b000000000;
|
||||
memory[4] <= 9'b000000000;
|
||||
memory[5] <= 9'b000000000;
|
||||
memory[6] <= 9'b000000000;
|
||||
memory[7] <= 9'b000000000;
|
||||
memory[8] <= 9'b000000000;
|
||||
memory[9] <= 9'b000000000;
|
||||
memory[10] <= 9'b000000000;
|
||||
memory[11] <= 9'b000000000;
|
||||
memory[12] <= 9'b000000000;
|
||||
memory[13] <= 9'b000000000;
|
||||
memory[14] <= 9'b000000000;
|
||||
memory[15] <= 9'b000000000;
|
||||
end
|
||||
|
||||
always@(address, posedge clk)begin
|
||||
if(clk == 1'b1)begin
|
||||
readData <= memory[address];
|
||||
if(writeEnable == 1'b1)begin
|
||||
memory[address] <= writeData;
|
||||
end
|
||||
else begin
|
||||
memory[address] <= memory[address];
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module dataMemory_tb();
|
||||
reg clk, writeEnable;
|
||||
reg [8:0] address, writeData;
|
||||
wire [8:0] readData;
|
||||
|
||||
initial begin
|
||||
clk = 1'b0;
|
||||
end
|
||||
always begin
|
||||
#5 clk = ~clk; // Period to be determined
|
||||
end
|
||||
|
||||
dataMemory dM0(
|
||||
.clk(clk),
|
||||
.writeEnable(writeEnable),
|
||||
.writeData(writeData),
|
||||
.address(address),
|
||||
.readData(readData)
|
||||
);
|
||||
|
||||
initial begin
|
||||
writeEnable = 1'b0;
|
||||
address = 9'b000000000;
|
||||
writeData = 9'b010101010;
|
||||
#5
|
||||
address = 9'b000000100;
|
||||
writeData = 9'b010101010;
|
||||
#10
|
||||
writeEnable = 1'b1;
|
||||
address = 9'b000000000;
|
||||
writeData = 9'b010101010;
|
||||
#10
|
||||
address = 9'b000000001;
|
||||
writeData = 9'b000001111;
|
||||
#10
|
||||
address = 9'b000000010;
|
||||
writeData = 9'b000000101;
|
||||
#10
|
||||
address = 9'b000000011;
|
||||
writeData = 9'b000000011;
|
||||
#10
|
||||
address = 9'b00000010;
|
||||
writeData = 9'b000001101;
|
||||
#5
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
||||
64
lab2CA.srcs/sources_1/new/instructionMemory.v
Normal file
64
lab2CA.srcs/sources_1/new/instructionMemory.v
Normal file
@@ -0,0 +1,64 @@
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module instructionMemory(
|
||||
input wire clk,
|
||||
input wire [8:0] address,
|
||||
output reg [8:0] readData
|
||||
);
|
||||
|
||||
reg [8:0] memory [512:0];
|
||||
|
||||
initial begin
|
||||
//Equation Solver
|
||||
memory[0] <= 9'b000100000;
|
||||
memory[1] <= 9'b000101000;
|
||||
memory[2] <= 9'b010100010;
|
||||
memory[3] <= 9'b111100000;
|
||||
memory[4] <= 9'b111100000;
|
||||
memory[5] <= 9'b000000000;
|
||||
end
|
||||
|
||||
|
||||
always@(address, posedge clk)begin
|
||||
readData <= memory[address];
|
||||
end
|
||||
endmodule
|
||||
|
||||
|
||||
module instructionMemory_tb();
|
||||
reg clk;
|
||||
reg [8:0] address;
|
||||
wire [8:0] readData;
|
||||
|
||||
initial begin
|
||||
clk = 1'b0;
|
||||
end
|
||||
always begin
|
||||
#5 clk = ~clk; // Period to be determined
|
||||
end
|
||||
|
||||
instructionMemory iM0(
|
||||
.clk(clk),
|
||||
.address(address),
|
||||
.readData(readData)
|
||||
);
|
||||
|
||||
initial begin
|
||||
#10
|
||||
address = 9'b000000000;
|
||||
#5
|
||||
address = 9'b000000001;
|
||||
#5
|
||||
address = 9'b000000010;
|
||||
#5
|
||||
address = 9'b000000011;
|
||||
#5
|
||||
address = 9'b000000100;
|
||||
#5
|
||||
address = 9'b000000101;
|
||||
#5
|
||||
address = 9'b000000111;
|
||||
#5
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
||||
28
lab2CA.xpr
28
lab2CA.xpr
@@ -3,7 +3,7 @@
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="39" Path="C:/Users/JoseIgnacio/CA Lab/lab2CA.xpr">
|
||||
<Project Version="7" Minor="39" Path="C:/Users/ecelab/ECE3570-Lab/lab2CA.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="0a5803efda44405bb28bbf43ba22e808"/>
|
||||
@@ -31,7 +31,7 @@
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="133"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="146"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
@@ -109,6 +109,22 @@
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/instructionMemory.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/dataMemory.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="CPU9bits"/>
|
||||
@@ -122,20 +138,14 @@
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/CPU9bits_tb_behav.wcfg">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="CPU9bits_tb"/>
|
||||
<Option Name="TopModule" Val="dataMemory_tb"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
<Option Name="XSimWcfgFile" Val="$PPRDIR/regFile_tb_behav.wcfg"/>
|
||||
<Option Name="XSimWcfgFile" Val="$PPRDIR/CPU9bits_tb_behav.wcfg"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
|
||||
Reference in New Issue
Block a user