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jose.rodriguezlabra eac5d71dd6 Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
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#	lab2CA.cache/wt/webtalk_pa.xml
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Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
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lab2CA.sim/sim_1
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Bank_behav1.wcfg
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CPU9bits_tb_behav.wcfg
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Replaced missing simulation configuration file
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README.md
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regFile_tb_behav.wcfg
Better Sim
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README.md

ECE 3570 Lab

Unknown Status of Fixes

  • Only two registers are being written to, first two within simulation is not being written to
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Description
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Readme 5.2 MiB
Languages
C 33.3%
Verilog 26.9%
PureBasic 23.7%
Tcl 16.1%