Minor changes to CPU

lab2CA.srcs/sources_1/new/CPU9bits.v

@@ -20,7 +20,7 @@ module CPU9bits(
         .clk(clk),
         .writeEnable(loadS),
         .writeData(op0),
-        .address(AluOut),
+        .address(op1),
         .readData(dataMemOut)
         );    
           

lab2CA.srcs/sources_1/new/dataMemory.v

@@ -27,10 +27,10 @@ module dataMemory(
         memory[15] <= 9'b000000000;
     end
 
-    always@(address, posedge clk)begin
+    always@(address)begin
         if(clk == 1'b1)begin
         readData <= memory[address];
-        if(writeEnable == 1'b1)begin
+        if(writeEnable == 1'b0)begin
         memory[address] <= writeData;
         end
         else begin

lab2CA.srcs/sources_1/new/instructionMemory.v

@@ -19,7 +19,7 @@ module instructionMemory(
     end
     
     
-    always@(address, posedge clk)begin
+    always@(address)begin
         readData <= memory[address];
     end
 endmodule