65b951cf82
# Conflicts: # Bank_behav1.wcfg # lab2CA.runs/.jobs/vrs_config_42.xml # lab2CA.runs/impl_1/CPU9bits_tb.tcl # lab2CA.runs/impl_1/gen_run.xml # lab2CA.runs/impl_1/htr.txt # lab2CA.runs/impl_1/init_design.pb # lab2CA.runs/impl_1/opt_design.pb # lab2CA.runs/impl_1/place_design.pb # lab2CA.runs/impl_1/vivado.jou # lab2CA.runs/impl_1/vivado.pb # lab2CA.runs/synth_1/CPU9bits.dcp # lab2CA.runs/synth_1/CPU9bits.vds # lab2CA.runs/synth_1/CPU9bits_tb.tcl # lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.rpt # lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb # lab2CA.runs/synth_1/gen_run.xml # lab2CA.runs/synth_1/vivado.jou # lab2CA.runs/synth_1/vivado.pb # lab2CA.sim/sim_1/behav/xsim/webtalk.jou # lab2CA.sim/sim_1/behav/xsim/webtalk_12056.backup.jou # lab2CA.sim/sim_1/behav/xsim/webtalk_15032.backup.jou # lab2CA.sim/sim_1/behav/xsim/xelab.pb # lab2CA.sim/sim_1/behav/xsim/xvlog.pb # lab2CA.srcs/sources_1/new/instructionMemory.v # lab2CA.xpr
ECE 3570 Lab
Unknown Status of Fixes
- Only two registers are being written to, first two within simulation is not being written to