William/WMU-ECE-3570-Lab
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jose.rodriguezlabra 27f6d24b88 Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	lab2CA.cache/wt/webtalk_pa.xml
#	lab2CA.runs/impl_1/gen_run.xml
#	lab2CA.runs/synth_1/gen_run.xml
#	lab2CA.sim/sim_1/behav/xsim/xelab.pb
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
#	lab2CA.sim/sim_1/behav/xsim/xvlog.pb
#	lab2CA.srcs/sources_1/new/instructionMemory.v
#	lab2CA.xpr
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lab2CA.cache/wt
stuff
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lab2CA.ip_user_files
fetch unit
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lab2CA.runs
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
2019-03-24 14:17:59 -04:00
lab2CA.sim/sim_1
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
2019-03-24 14:17:59 -04:00
lab2CA.srcs/sources_1
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
2019-03-24 14:17:59 -04:00
.gitignore
Excluded Markdown files
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Bank_behav1.wcfg
Added bank to CPU9bits
2019-03-24 12:11:12 -04:00
CPU9bits_tb_behav.wcfg
BEQ Opcode fix & other stuffz
2019-03-22 19:54:06 -04:00
lab2CA.xpr
stuff
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README.md
Updated README
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regFile_tb_behav.wcfg
Better Sim
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vivado_10872.backup.jou
stuff
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vivado_15076.backup.jou
new thing
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vivado_15356.backup.jou
more stuff
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vivado.jou
new thing
2019-02-16 13:04:06 -05:00

README.md

ECE 3570 Lab

Unknown Status of Fixes

  • Only two registers are being written to, first two within simulation is not being written to
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Description
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Readme 5.2 MiB
Languages
C 33.3%
Verilog 26.9%
PureBasic 23.7%
Tcl 16.1%