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jose.rodriguezlabra 5a506ba3ab Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2

# Conflicts:
#	lab2CA.cache/wt/webtalk_pa.xml
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
#	lab2CA.srcs/sources_1/new/instructionMemory.v
#	lab2CA.xpr

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lab2CA.cache/wt

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lab2CA.ip_user_files

fetch unit

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lab2CA.runs

String Compare Working

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lab2CA.sim/sim_1

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lab2CA.srcs/sources_1

Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2

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.gitignore

Excluded Markdown files

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Bank_behav1.wcfg

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CPU9bits_tb_behav.wcfg

BEQ and LD fix

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lab2CA.xpr

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README.md

Updated README

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regFile_tb_behav.wcfg

Better Sim

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StringCompare.wcfg

String Compare Working

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vivado_10872.backup.jou

stuff

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vivado_15076.backup.jou

new thing

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vivado_15356.backup.jou

more stuff

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vivado.jou

new thing

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README.md

ECE 3570 Lab

Unknown Status of Fixes

Only two registers are being written to, first two within simulation is not being written to