Now Asynchronous and recognized by Vivado as RTL_ROM

2019-03-29 16:13:07 -04:00
parent 5c165d603a
commit 5bd244f9ba
1 changed files with 2 additions and 5 deletions
--- a/lab2CA.srcs/sources_1/new/instructionMemory.v
+++ b/lab2CA.srcs/sources_1/new/instructionMemory.v
@@ -210,11 +210,8 @@ module instructionMemory(
 
    end
    
-    always@(address, clk)begin
-        if(clk == 1'b1)begin
-            readData <= memory[address];
-        end
-    end
+    always @ (address)
+        readData <= memory[address];
 endmodule