452 lines
23 KiB
Plaintext
452 lines
23 KiB
Plaintext
#-----------------------------------------------------------
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# Vivado v2018.3 (64-bit)
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# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
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# Start of session at: Sat Feb 16 17:35:59 2019
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# Process ID: 3548
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# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1
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# Command line: vivado.exe -log FetchUnit.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source FetchUnit.tcl -notrace
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# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit.vdi
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# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1\vivado.jou
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#-----------------------------------------------------------
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source FetchUnit.tcl -notrace
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Command: link_design -top FetchUnit -part xc7k160tifbg484-2L
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Design is defaulting to srcset: sources_1
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Design is defaulting to constrset: constrs_1
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INFO: [Project 1-479] Netlist was created with Vivado 2018.3
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INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
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INFO: [Project 1-570] Preparing netlist for logic optimization
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 578.453 ; gain = 0.000
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INFO: [Project 1-111] Unisim Transformation Summary:
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No Unisim elements were transformed.
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4 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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link_design completed successfully
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link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:16 . Memory (MB): peak = 584.031 ; gain = 333.246
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Command: opt_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
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Running DRC as a precondition to command opt_design
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Starting DRC Task
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Project 1-461] DRC finished with 0 Errors
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INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.760 . Memory (MB): peak = 598.289 ; gain = 14.258
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Starting Cache Timing Information Task
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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Ending Cache Timing Information Task | Checksum: 3da38fa8
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Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1160.113 ; gain = 561.824
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Starting Logic Optimization Task
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Phase 1 Retarget
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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INFO: [Opt 31-49] Retargeted 0 cell(s).
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Phase 1 Retarget | Checksum: 3da38fa8
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1256.469 ; gain = 0.000
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INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
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Phase 2 Constant propagation
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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Phase 2 Constant propagation | Checksum: 3da38fa8
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1256.469 ; gain = 0.000
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INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
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Phase 3 Sweep
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Phase 3 Sweep | Checksum: 3da38fa8
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 1256.469 ; gain = 0.000
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INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
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Phase 4 BUFG optimization
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Phase 4 BUFG optimization | Checksum: 3da38fa8
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.059 . Memory (MB): peak = 1256.469 ; gain = 0.000
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INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
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Phase 5 Shift Register Optimization
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Phase 5 Shift Register Optimization | Checksum: 3da38fa8
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.095 . Memory (MB): peak = 1256.469 ; gain = 0.000
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INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
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Phase 6 Post Processing Netlist
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Phase 6 Post Processing Netlist | Checksum: 3da38fa8
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.096 . Memory (MB): peak = 1256.469 ; gain = 0.000
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INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
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Opt_design Change Summary
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=========================
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-------------------------------------------------------------------------------------------------------------------------
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| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
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-------------------------------------------------------------------------------------------------------------------------
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| Retarget | 0 | 0 | 0 |
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| Constant propagation | 0 | 0 | 0 |
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| Sweep | 0 | 0 | 0 |
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| BUFG optimization | 0 | 0 | 0 |
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| Shift Register Optimization | 0 | 0 | 0 |
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| Post Processing Netlist | 0 | 0 | 0 |
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-------------------------------------------------------------------------------------------------------------------------
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Starting Connectivity Check Task
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1256.469 ; gain = 0.000
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Ending Logic Optimization Task | Checksum: 3da38fa8
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.098 . Memory (MB): peak = 1256.469 ; gain = 0.000
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Starting Power Optimization Task
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INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
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Ending Power Optimization Task | Checksum: 3da38fa8
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1256.469 ; gain = 0.000
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Starting Final Cleanup Task
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Ending Final Cleanup Task | Checksum: 3da38fa8
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1256.469 ; gain = 0.000
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Starting Netlist Obfuscation Task
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1256.469 ; gain = 0.000
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Ending Netlist Obfuscation Task | Checksum: 3da38fa8
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1256.469 ; gain = 0.000
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INFO: [Common 17-83] Releasing license: Implementation
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20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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opt_design completed successfully
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opt_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1256.469 ; gain = 672.438
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1256.469 ; gain = 0.000
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WARNING: [Constraints 18-5210] No constraints selected for write.
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Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
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INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit_opt.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_drc -file FetchUnit_drc_opted.rpt -pb FetchUnit_drc_opted.pb -rpx FetchUnit_drc_opted.rpx
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Command: report_drc -file FetchUnit_drc_opted.rpt -pb FetchUnit_drc_opted.pb -rpx FetchUnit_drc_opted.rpx
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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INFO: [IP_Flow 19-1704] No user IP repositories specified
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INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.3/data/ip'.
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit_drc_opted.rpt.
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report_drc completed successfully
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Command: place_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Running DRC as a precondition to command place_design
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Starting Placer Task
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INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
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Phase 1 Placer Initialization
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Phase 1.1 Placer Initialization Netlist Sorting
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1256.469 ; gain = 0.000
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Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2dee624c
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1256.469 ; gain = 0.000
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1256.469 ; gain = 0.000
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Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: c3ac8419
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1260.031 ; gain = 3.563
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Phase 1.3 Build Placer Netlist Model
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Phase 1.3 Build Placer Netlist Model | Checksum: 17eb8b195
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1260.031 ; gain = 3.563
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Phase 1.4 Constrain Clocks/Macros
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Phase 1.4 Constrain Clocks/Macros | Checksum: 17eb8b195
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1260.031 ; gain = 3.563
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Phase 1 Placer Initialization | Checksum: 17eb8b195
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1260.031 ; gain = 3.563
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Phase 2 Global Placement
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Phase 2.1 Floorplanning
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Phase 2.1 Floorplanning | Checksum: 17eb8b195
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1261.789 ; gain = 5.320
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WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
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Phase 2 Global Placement | Checksum: c93401db
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1270.621 ; gain = 14.152
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Phase 3 Detail Placement
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Phase 3.1 Commit Multi Column Macros
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Phase 3.1 Commit Multi Column Macros | Checksum: c93401db
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1270.621 ; gain = 14.152
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Phase 3.2 Commit Most Macros & LUTRAMs
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Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 13d5628d5
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1270.621 ; gain = 14.152
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Phase 3.3 Area Swap Optimization
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Phase 3.3 Area Swap Optimization | Checksum: 1566ae30c
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1270.621 ; gain = 14.152
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Phase 3.4 Pipeline Register Optimization
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Phase 3.4 Pipeline Register Optimization | Checksum: 1566ae30c
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1270.621 ; gain = 14.152
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Phase 3.5 Small Shape Detail Placement
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Phase 3.5 Small Shape Detail Placement | Checksum: 179d3e6f9
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980
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Phase 3.6 Re-assign LUT pins
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Phase 3.6 Re-assign LUT pins | Checksum: 179d3e6f9
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980
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Phase 3.7 Pipeline Register Optimization
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Phase 3.7 Pipeline Register Optimization | Checksum: 179d3e6f9
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980
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Phase 3 Detail Placement | Checksum: 179d3e6f9
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980
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Phase 4 Post Placement Optimization and Clean-Up
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Phase 4.1 Post Commit Optimization
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Phase 4.1 Post Commit Optimization | Checksum: 179d3e6f9
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980
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Phase 4.2 Post Placement Cleanup
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Phase 4.2 Post Placement Cleanup | Checksum: 179d3e6f9
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980
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Phase 4.3 Placer Reporting
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Phase 4.3 Placer Reporting | Checksum: 179d3e6f9
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980
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Phase 4.4 Final Placement Cleanup
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1280.449 ; gain = 0.000
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Phase 4.4 Final Placement Cleanup | Checksum: 1f8cde3fa
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980
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Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1f8cde3fa
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980
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Ending Placer Task | Checksum: 12070b279
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Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980
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INFO: [Common 17-83] Releasing license: Implementation
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37 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
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place_design completed successfully
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1280.449 ; gain = 0.000
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WARNING: [Constraints 18-5210] No constraints selected for write.
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Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
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Writing placer database...
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Writing XDEF routing.
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Writing XDEF routing logical nets.
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Writing XDEF routing special nets.
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Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.094 . Memory (MB): peak = 1280.449 ; gain = 0.000
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INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit_placed.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_io -file FetchUnit_io_placed.rpt
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report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.056 . Memory (MB): peak = 1280.449 ; gain = 0.000
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INFO: [runtcl-4] Executing : report_utilization -file FetchUnit_utilization_placed.rpt -pb FetchUnit_utilization_placed.pb
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INFO: [runtcl-4] Executing : report_control_sets -verbose -file FetchUnit_control_sets_placed.rpt
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report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1280.449 ; gain = 0.000
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Command: route_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
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Running DRC as a precondition to command route_design
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Starting Routing Task
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INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
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Checksum: PlaceDB: 80d46943 ConstDB: 0 ShapeSum: 9f9c4936 RouteDB: 0
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Phase 1 Build RT Design
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Phase 1 Build RT Design | Checksum: c942aae2
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Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 1491.852 ; gain = 211.402
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Post Restoration Checksum: NetGraph: 96738515 NumContArr: 32cf25cd Constraints: 0 Timing: 0
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Phase 2 Router Initialization
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INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
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Phase 2.1 Fix Topology Constraints
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Phase 2.1 Fix Topology Constraints | Checksum: c942aae2
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Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 1496.797 ; gain = 216.348
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Phase 2.2 Pre Route Cleanup
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Phase 2.2 Pre Route Cleanup | Checksum: c942aae2
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Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 1496.797 ; gain = 216.348
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Number of Nodes with overlaps = 0
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Phase 2 Router Initialization | Checksum: a27c41a8
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Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 1520.801 ; gain = 240.352
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Phase 3 Initial Routing
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Phase 3 Initial Routing | Checksum: 15301da77
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Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352
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Phase 4 Rip-up And Reroute
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Phase 4.1 Global Iteration 0
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Number of Nodes with overlaps = 1
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Number of Nodes with overlaps = 0
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Phase 4.1 Global Iteration 0 | Checksum: af31d432
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Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352
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Phase 4 Rip-up And Reroute | Checksum: af31d432
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Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352
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Phase 5 Delay and Skew Optimization
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Phase 5 Delay and Skew Optimization | Checksum: af31d432
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Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352
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Phase 6 Post Hold Fix
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Phase 6.1 Hold Fix Iter
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Phase 6.1 Hold Fix Iter | Checksum: af31d432
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Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352
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Phase 6 Post Hold Fix | Checksum: af31d432
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Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352
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Phase 7 Route finalize
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Router Utilization Summary
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Global Vertical Routing Utilization = 0.00297689 %
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Global Horizontal Routing Utilization = 0.00221654 %
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Routable Net Status*
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*Does not include unroutable nets such as driverless and loadless.
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Run report_route_status for detailed report.
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Number of Failed Nets = 0
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Number of Unrouted Nets = 0
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Number of Partially Routed Nets = 0
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Number of Node Overlaps = 0
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Congestion Report
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North Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions.
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South Dir 1x1 Area, Max Cong = 25.2252%, No Congested Regions.
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East Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions.
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West Dir 1x1 Area, Max Cong = 16.1765%, No Congested Regions.
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------------------------------
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Reporting congestion hotspots
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------------------------------
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Direction: North
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----------------
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Congested clusters found at Level 0
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Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
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Direction: South
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----------------
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Congested clusters found at Level 0
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Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
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Direction: East
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----------------
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Congested clusters found at Level 0
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Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
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Direction: West
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----------------
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Congested clusters found at Level 0
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Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
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Phase 7 Route finalize | Checksum: af31d432
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Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352
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Phase 8 Verifying routed nets
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Verification completed successfully
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Phase 8 Verifying routed nets | Checksum: af31d432
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Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352
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Phase 9 Depositing Routes
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Phase 9 Depositing Routes | Checksum: 4b1641fa
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Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352
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INFO: [Route 35-16] Router Completed Successfully
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Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352
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Routing Is Done.
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INFO: [Common 17-83] Releasing license: Implementation
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49 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
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route_design completed successfully
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route_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:31 . Memory (MB): peak = 1520.801 ; gain = 240.352
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1520.801 ; gain = 0.000
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WARNING: [Constraints 18-5210] No constraints selected for write.
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Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
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Writing placer database...
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Writing XDEF routing.
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Writing XDEF routing logical nets.
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Writing XDEF routing special nets.
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Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1520.801 ; gain = 0.000
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INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit_routed.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_drc -file FetchUnit_drc_routed.rpt -pb FetchUnit_drc_routed.pb -rpx FetchUnit_drc_routed.rpx
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Command: report_drc -file FetchUnit_drc_routed.rpt -pb FetchUnit_drc_routed.pb -rpx FetchUnit_drc_routed.rpx
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INFO: [IP_Flow 19-1839] IP Catalog is up to date.
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit_drc_routed.rpt.
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report_drc completed successfully
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INFO: [runtcl-4] Executing : report_methodology -file FetchUnit_methodology_drc_routed.rpt -pb FetchUnit_methodology_drc_routed.pb -rpx FetchUnit_methodology_drc_routed.rpx
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Command: report_methodology -file FetchUnit_methodology_drc_routed.rpt -pb FetchUnit_methodology_drc_routed.pb -rpx FetchUnit_methodology_drc_routed.rpx
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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INFO: [DRC 23-133] Running Methodology with 2 threads
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INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit_methodology_drc_routed.rpt.
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report_methodology completed successfully
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INFO: [runtcl-4] Executing : report_power -file FetchUnit_power_routed.rpt -pb FetchUnit_power_summary_routed.pb -rpx FetchUnit_power_routed.rpx
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Command: report_power -file FetchUnit_power_routed.rpt -pb FetchUnit_power_summary_routed.pb -rpx FetchUnit_power_routed.rpx
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WARNING: [Power 33-232] No user defined clocks were found in the design!
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Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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Running Vector-less Activity Propagation...
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Finished Running Vector-less Activity Propagation
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60 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
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report_power completed successfully
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INFO: [runtcl-4] Executing : report_route_status -file FetchUnit_route_status.rpt -pb FetchUnit_route_status.pb
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INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file FetchUnit_timing_summary_routed.rpt -pb FetchUnit_timing_summary_routed.pb -rpx FetchUnit_timing_summary_routed.rpx -warn_on_violation
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INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max.
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INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
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WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
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INFO: [runtcl-4] Executing : report_incremental_reuse -file FetchUnit_incremental_reuse_routed.rpt
|
|
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
|
|
INFO: [runtcl-4] Executing : report_clock_utilization -file FetchUnit_clock_utilization_routed.rpt
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INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file FetchUnit_bus_skew_routed.rpt -pb FetchUnit_bus_skew_routed.pb -rpx FetchUnit_bus_skew_routed.rpx
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INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max.
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INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
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INFO: [Common 17-206] Exiting Vivado at Sat Feb 16 17:37:11 2019...
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