WilliamMiceli 71c6c2ad55 Fixed indentations

2019-03-29 17:28:50 -04:00

..

ALU.v

Fixed unconnected wires

2019-03-29 17:21:29 -04:00

BasicModules.v

Fixed unconnected wires/ports

2019-03-29 17:22:06 -04:00

ControlUnit.v

Fixed indentations

2019-03-29 17:28:50 -04:00

CPU9bits.v

Formatted things to look a little nicer

2019-03-29 17:23:26 -04:00

dataMemory.v

Increased memory size to get rid of unused address ports warning

2019-03-29 17:23:00 -04:00

FetchUnit.v

Better Sim

2019-03-14 14:37:58 -04:00

instructionMemory.v

Removed references to CLK, as not needed; simplified testbench a little

2019-03-29 16:15:47 -04:00

RegFile.v

Fixed bugs, finished BEQ, Added Halt

2019-03-13 11:14:52 -04:00