75 lines
2.1 KiB
Verilog
75 lines
2.1 KiB
Verilog
`timescale 1ns / 1ps
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module ControlUnit(
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input wire [3:0] instIn,
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input wire functBit,
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output reg [2:0] aluOut,
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output reg [2:0] FU,
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output reg addi,
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output reg mem,
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output reg load,
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output reg RegEn
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);
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always @(instIn)begin
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case(instIn)
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4'b0101:
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if(functBit == 1) begin
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aluOut <= 3'b001; //sub
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RegEn <= 1'b0;
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end
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else begin
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aluOut <= 3'b000; //Add
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RegEn <= 1'b0;
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end
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4'b0111: begin
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aluOut <= 3'b111; //nor
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RegEn <= 1'b0;
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end
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4'b1110:
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if(functBit == 1) begin
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aluOut <= 3'b100; //and
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RegEn <= 1'b0;
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end
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else begin
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aluOut <= 3'b010; //or
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RegEn <= 1'b0;
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end
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4'b1111:
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if(functBit == 1) begin
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aluOut <= 3'b110; //srl
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RegEn <= 1'b0;
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end
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else begin
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aluOut <= 3'b101; //sll
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RegEn <= 1'b0;
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end
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4'b0110: begin
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addi <= 1'b1; // addi
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RegEn <= 1'b0;
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end
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4'b1001: begin
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FU <= 3'b010; // jump
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RegEn <= 1'b1;
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end
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4'b1100: begin
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FU <= 3'b011; // branch
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RegEn <= 1'b1;
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end
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4'b1000: begin
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FU <= 3'b001; // jumpreg
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RegEn <= 1'b1;
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end
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4'b0001: begin
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mem <= 1'b0; // load
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RegEn <= 1'b0;
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end
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4'b0010: begin
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mem <= 1'b1; // store
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RegEn <= 1'b1;
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end
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default: aluOut <= 3'bxxxx;
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endcase
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end
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endmodule
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