17 lines
607 B
Plaintext
17 lines
607 B
Plaintext
# compile verilog/system verilog design source files
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verilog xil_defaultlib \
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"../../../../lab2CA.srcs/sources_1/new/ALU.v" \
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"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \
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"../../../../lab2CA.srcs/sources_1/new/ControlUnit.v" \
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"../../../../lab2CA.srcs/sources_1/new/FetchUnit.v" \
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"../../../../lab2CA.srcs/sources_1/new/RegFile.v" \
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"../../../../lab2CA.srcs/sources_1/new/dataMemory.v" \
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"../../../../lab2CA.srcs/sources_1/new/instructionMemory.v" \
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"../../../../lab2CA.srcs/sources_1/new/CPU9bits.v" \
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# compile glbl module
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verilog xil_defaultlib "glbl.v"
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# Do not sort compile order
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nosort
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