William/WMU-ECE-3570-Lab
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WMU-ECE-3570-Lab/lab2CA.sim/sim_1/behav/xsim
History
WilliamMiceli de8740a231 Vivado runs/sim
2019-04-06 14:16:26 -04:00
..
xsim.dir
Vivado runs/sim
2019-04-06 14:16:26 -04:00
add1bit_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
add1bit_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
add9bit_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
add9bit_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
alu_tb_vlog.prj
Lots
2019-02-16 17:40:18 -05:00
alu_tb.tcl
Lots
2019-02-16 17:40:18 -05:00
ALU_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
ALU.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
and1bit_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
and1bit_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
and9bit_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
and9bit_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
comparator_tb_vlog.prj
Many Changes
2019-03-12 21:14:27 -04:00
comparator_tb.tcl
Many Changes
2019-03-12 21:14:27 -04:00
CPU9bits_tb_vlog.prj
Tested the instructions using the instruction memory
2019-03-20 12:08:24 -04:00
CPU9bits_tb.tcl
Making fixes to Bubble Sort
2019-03-24 19:27:59 -04:00
CPU9bits_vlog.prj
Vivado runs/sim
2019-04-06 14:16:26 -04:00
CPU9bits.tcl
Vivado runs/sim
2019-04-06 14:16:26 -04:00
dataMemory_tb_vlog.prj
Instruction & Data Memory
2019-03-16 14:16:02 -04:00
dataMemory_tb.tcl
Vivado stuff
2019-03-29 17:29:24 -04:00
decoder_tb_vlog.prj
Lots of changes
2019-02-27 12:06:17 -05:00
decoder_tb.tcl
Lots of changes
2019-02-27 12:06:17 -05:00
fetchUnit_tb_vlog.prj
fetch unit test
2019-02-20 11:31:25 -05:00
fetchUnit_tb.tcl
fetch unit test
2019-02-20 11:31:25 -05:00
glbl.v
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
instructionMemory_tb_vlog.prj
Instruction & Data Memory
2019-03-16 14:16:02 -04:00
instructionMemory_tb.tcl
Instruction & Data Memory
2019-03-16 14:16:02 -04:00
mux_2_1_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
mux_2_1_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
mux_4_1_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
mux_4_1_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
mux_8_1_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
mux_8_1_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
nor_1bit_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
nor_1bit_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
nor_9bit_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
nor_9bit_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
not_1bit_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
not_1bit_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
not_9bit_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
not_9bit_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
or_1bit_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
or_1bit_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
or_9bit_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
or_9bit_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
regFile_tb_vlog.prj
Lots
2019-02-16 17:40:18 -05:00
regFile_tb.tcl
Lots
2019-02-16 17:40:18 -05:00
register_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
register_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
shift_logical_left_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
shift_logical_left_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
shift_logical_right_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
shift_logical_right_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
slt_tb_vlog.prj
Added SLT
2019-03-12 19:49:46 -04:00
slt_tb.tcl
Added SLT
2019-03-12 19:49:46 -04:00
sub_9bit_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
sub_9bit_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
twos_compliment_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
twos_compliment_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
webtalk_5080.backup.jou
Vivado stuff
2019-03-29 17:29:24 -04:00
webtalk_11564.backup.jou
Vivado runs/sim
2019-04-06 14:16:26 -04:00
webtalk_14652.backup.jou
Vivado stuff
2019-03-29 17:29:24 -04:00
webtalk_26660.backup.jou
Vivado stuff
2019-03-29 17:29:24 -04:00
webtalk_28052.backup.jou
Vivado runs/sim
2019-04-06 14:16:26 -04:00
webtalk.jou
Vivado runs/sim
2019-04-06 14:16:26 -04:00
xelab.pb
Vivado runs/sim
2019-04-06 14:16:26 -04:00
xvlog.pb
Vivado runs/sim
2019-04-06 14:16:26 -04:00