429 lines
32 KiB
Plaintext
429 lines
32 KiB
Plaintext
#-----------------------------------------------------------
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# Vivado v2018.3 (64-bit)
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# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
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# Start of session at: Wed Apr 10 12:49:25 2019
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# Process ID: 13540
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# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1
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# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
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# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds
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# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou
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#-----------------------------------------------------------
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source CPU9bits.tcl -notrace
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Command: synth_design -top CPU9bits -part xc7k160tifbg484-2L
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Starting synth_design
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Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti'
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INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti'
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INFO: Launching helper process for spawning children vivado processes
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INFO: Helper process launched with PID 17664
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---------------------------------------------------------------------------------
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Starting Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 362.465 ; gain = 101.664
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---------------------------------------------------------------------------------
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INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
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INFO: [Synth 8-6157] synthesizing module 'FDModule' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FDModule.v:3]
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INFO: [Synth 8-6157] synthesizing module 'instructionMemory' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'instructionMemory' (1#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
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INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
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INFO: [Synth 8-6157] synthesizing module 'register' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:773]
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INFO: [Synth 8-6155] done synthesizing module 'register' (2#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:773]
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INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
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INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (3#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (4#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
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INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:332]
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INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:338]
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INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (5#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:332]
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INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (6#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
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INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
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INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
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INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:268]
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INFO: [Synth 8-6155] done synthesizing module 'decoder' (7#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
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INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:403]
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INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:408]
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INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (8#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:403]
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INFO: [Synth 8-6155] done synthesizing module 'RegFile' (9#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
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INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
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INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:14]
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INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (10#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'FDModule' (11#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FDModule.v:3]
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INFO: [Synth 8-6157] synthesizing module 'fDPipReg' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:849]
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INFO: [Synth 8-6155] done synthesizing module 'fDPipReg' (12#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:849]
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INFO: [Synth 8-6157] synthesizing module 'EMModule' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/EMModule.v:5]
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INFO: [Synth 8-6157] synthesizing module 'dataMemory' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'dataMemory' (13#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
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INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
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INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1341]
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INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1406]
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INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:683]
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INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (14#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:683]
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INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (15#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1406]
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INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (16#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1341]
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INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:720]
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INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (17#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:720]
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INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:639]
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INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (18#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:639]
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INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
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INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (19#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
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INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:883]
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INFO: [Synth 8-6155] done synthesizing module 'shift_left' (20#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:883]
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INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:957]
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INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (21#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:957]
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INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:920]
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INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (22#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:920]
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INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:316]
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INFO: [Synth 8-6155] done synthesizing module 'less_than' (23#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:316]
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INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1455]
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INFO: [Synth 8-6155] done synthesizing module 'BEQ' (24#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1455]
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INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:531]
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INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:537]
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INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (25#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:531]
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INFO: [Synth 8-6155] done synthesizing module 'ALU' (26#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
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INFO: [Synth 8-6157] synthesizing module 'sign_extend_3bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1026]
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INFO: [Synth 8-6155] done synthesizing module 'sign_extend_3bit' (27#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1026]
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INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:346]
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INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:352]
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INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (28#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:346]
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INFO: [Synth 8-6155] done synthesizing module 'EMModule' (29#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/EMModule.v:5]
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INFO: [Synth 8-6157] synthesizing module 'eMPipReg' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:866]
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INFO: [Synth 8-6155] done synthesizing module 'eMPipReg' (30#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:866]
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INFO: [Synth 8-6157] synthesizing module 'WMUdule' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/WMUdule.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'WMUdule' (31#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/WMUdule.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (32#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
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WARNING: [Synth 8-3331] design dataMemory has unconnected port address[8]
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WARNING: [Synth 8-3331] design dataMemory has unconnected port address[7]
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WARNING: [Synth 8-3331] design EMModule has unconnected port PipIn[50]
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WARNING: [Synth 8-3331] design EMModule has unconnected port PipIn[49]
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WARNING: [Synth 8-3331] design EMModule has unconnected port PipIn[48]
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WARNING: [Synth 8-3331] design EMModule has unconnected port PipIn[47]
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---------------------------------------------------------------------------------
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Finished Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 418.434 ; gain = 157.633
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 418.434 ; gain = 157.633
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Loading Part and Timing Information
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---------------------------------------------------------------------------------
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Loading part: xc7k160tifbg484-2L
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---------------------------------------------------------------------------------
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 418.434 ; gain = 157.633
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---------------------------------------------------------------------------------
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INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
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---------------------------------------------------------------------------------
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Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 418.434 ; gain = 157.633
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---------------------------------------------------------------------------------
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INFO: [Synth 8-223] decloning instance 'EM/SE1' (sign_extend_3bit) to 'EM/SE3'
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Report RTL Partitions:
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+-+--------------+------------+----------+
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| |RTL Partition |Replication |Instances |
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+-+--------------+------------+----------+
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+-+--------------+------------+----------+
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No constraint files found.
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---------------------------------------------------------------------------------
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Start RTL Component Statistics
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---------------------------------------------------------------------------------
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Detailed RTL Component Info :
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+---XORs :
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2 Input 1 Bit XORs := 162
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+---Registers :
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62 Bit Registers := 1
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51 Bit Registers := 1
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9 Bit Registers := 10
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+---RAMs :
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909 Bit RAMs := 1
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+---Muxes :
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2 Input 9 Bit Muxes := 8
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4 Input 9 Bit Muxes := 4
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2 Input 4 Bit Muxes := 2
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4 Input 4 Bit Muxes := 2
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16 Input 4 Bit Muxes := 1
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2 Input 3 Bit Muxes := 2
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16 Input 3 Bit Muxes := 1
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16 Input 2 Bit Muxes := 1
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16 Input 1 Bit Muxes := 7
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2 Input 1 Bit Muxes := 1
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---------------------------------------------------------------------------------
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Finished RTL Component Statistics
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start RTL Hierarchical Component Statistics
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---------------------------------------------------------------------------------
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Hierarchical RTL Component report
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Module register
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Detailed RTL Component Info :
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+---Registers :
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9 Bit Registers := 1
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Module add_1bit
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Detailed RTL Component Info :
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+---XORs :
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2 Input 1 Bit XORs := 2
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Module mux_2_1
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Detailed RTL Component Info :
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+---Muxes :
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2 Input 9 Bit Muxes := 1
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Module decoder
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Detailed RTL Component Info :
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+---Muxes :
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2 Input 4 Bit Muxes := 1
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4 Input 4 Bit Muxes := 1
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Module mux_4_1
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Detailed RTL Component Info :
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+---Muxes :
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4 Input 9 Bit Muxes := 1
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Module ControlUnit
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Detailed RTL Component Info :
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+---Muxes :
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16 Input 4 Bit Muxes := 1
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2 Input 3 Bit Muxes := 2
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16 Input 3 Bit Muxes := 1
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16 Input 2 Bit Muxes := 1
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16 Input 1 Bit Muxes := 7
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Module fDPipReg
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Detailed RTL Component Info :
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+---Registers :
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51 Bit Registers := 1
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Module dataMemory
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Detailed RTL Component Info :
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+---Registers :
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9 Bit Registers := 1
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+---RAMs :
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909 Bit RAMs := 1
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Module bit1_mux_2_1
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Detailed RTL Component Info :
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+---Muxes :
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2 Input 1 Bit Muxes := 1
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Module eMPipReg
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Detailed RTL Component Info :
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+---Registers :
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62 Bit Registers := 1
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---------------------------------------------------------------------------------
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Finished RTL Hierarchical Component Statistics
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Part Resource Summary
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---------------------------------------------------------------------------------
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Part Resources:
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DSPs: 600 (col length:100)
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BRAMs: 650 (col length: RAMB18 100 RAMB36 50)
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---------------------------------------------------------------------------------
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Finished Part Resource Summary
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---------------------------------------------------------------------------------
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No constraint files found.
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---------------------------------------------------------------------------------
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Start Cross Boundary and Area Optimization
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---------------------------------------------------------------------------------
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Warning: Parallel synthesis criteria is not met
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---------------------------------------------------------------------------------
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Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 594.785 ; gain = 333.984
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start ROM, RAM, DSP and Shift Register Reporting
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---------------------------------------------------------------------------------
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ROM:
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+------------------+------------+---------------+----------------+
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|Module Name | RTL Object | Depth x Width | Implemented As |
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+------------------+------------+---------------+----------------+
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|instructionMemory | p_0_out | 64x9 | LUT |
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|CPU9bits | p_0_out | 64x9 | LUT |
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+------------------+------------+---------------+----------------+
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Block RAM: Preliminary Mapping Report (see note below)
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+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
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|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
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+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
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|dataMemory: | memory_reg | 128 x 9(NO_CHANGE) | W | R | | | | Port A | 1 | 0 |
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+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
|
|
|
Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.
|
|
---------------------------------------------------------------------------------
|
|
Finished ROM, RAM, DSP and Shift Register Reporting
|
|
---------------------------------------------------------------------------------
|
|
|
|
Report RTL Partitions:
|
|
+-+--------------+------------+----------+
|
|
| |RTL Partition |Replication |Instances |
|
|
+-+--------------+------------+----------+
|
|
+-+--------------+------------+----------+
|
|
No constraint files found.
|
|
---------------------------------------------------------------------------------
|
|
Start Timing Optimization
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Timing Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 594.785 ; gain = 333.984
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start ROM, RAM, DSP and Shift Register Reporting
|
|
---------------------------------------------------------------------------------
|
|
|
|
Block RAM: Final Mapping Report
|
|
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
|
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
|
|
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
|
|dataMemory: | memory_reg | 128 x 9(NO_CHANGE) | W | R | | | | Port A | 1 | 0 |
|
|
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
|
|
|
---------------------------------------------------------------------------------
|
|
Finished ROM, RAM, DSP and Shift Register Reporting
|
|
---------------------------------------------------------------------------------
|
|
|
|
Report RTL Partitions:
|
|
+-+--------------+------------+----------+
|
|
| |RTL Partition |Replication |Instances |
|
|
+-+--------------+------------+----------+
|
|
+-+--------------+------------+----------+
|
|
---------------------------------------------------------------------------------
|
|
Start Technology Mapping
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Technology Mapping : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 594.785 ; gain = 333.984
|
|
---------------------------------------------------------------------------------
|
|
|
|
Report RTL Partitions:
|
|
+-+--------------+------------+----------+
|
|
| |RTL Partition |Replication |Instances |
|
|
+-+--------------+------------+----------+
|
|
+-+--------------+------------+----------+
|
|
---------------------------------------------------------------------------------
|
|
Start IO Insertion
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Flattening Before IO Insertion
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Flattening Before IO Insertion
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Final Netlist Cleanup
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Final Netlist Cleanup
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished IO Insertion : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
|
|
---------------------------------------------------------------------------------
|
|
|
|
Report Check Netlist:
|
|
+------+------------------+-------+---------+-------+------------------+
|
|
| |Item |Errors |Warnings |Status |Description |
|
|
+------+------------------+-------+---------+-------+------------------+
|
|
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
|
+------+------------------+-------+---------+-------+------------------+
|
|
---------------------------------------------------------------------------------
|
|
Start Renaming Generated Instances
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Renaming Generated Instances : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
|
|
---------------------------------------------------------------------------------
|
|
|
|
Report RTL Partitions:
|
|
+-+--------------+------------+----------+
|
|
| |RTL Partition |Replication |Instances |
|
|
+-+--------------+------------+----------+
|
|
+-+--------------+------------+----------+
|
|
---------------------------------------------------------------------------------
|
|
Start Rebuilding User Hierarchy
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Renaming Generated Ports
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Renaming Generated Ports : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Handling Custom Attributes
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Handling Custom Attributes : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Renaming Generated Nets
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Renaming Generated Nets : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Writing Synthesis Report
|
|
---------------------------------------------------------------------------------
|
|
|
|
Report BlackBoxes:
|
|
+-+--------------+----------+
|
|
| |BlackBox name |Instances |
|
|
+-+--------------+----------+
|
|
+-+--------------+----------+
|
|
|
|
Report Cell Usage:
|
|
+------+---------+------+
|
|
| |Cell |Count |
|
|
+------+---------+------+
|
|
|1 |BUFG | 1|
|
|
|2 |LUT1 | 2|
|
|
|3 |LUT2 | 9|
|
|
|4 |LUT3 | 22|
|
|
|5 |LUT4 | 25|
|
|
|6 |LUT5 | 42|
|
|
|7 |LUT6 | 101|
|
|
|8 |MUXF7 | 1|
|
|
|9 |RAMB18E1 | 1|
|
|
|10 |FDRE | 181|
|
|
|11 |IBUF | 2|
|
|
|12 |OBUF | 10|
|
|
+------+---------+------+
|
|
|
|
Report Instance Areas:
|
|
+------+-----------+------------+------+
|
|
| |Instance |Module |Cells |
|
|
+------+-----------+------------+------+
|
|
|1 |top | | 397|
|
|
|2 | EM |EMModule | 46|
|
|
|3 | Bank |RegFile_4 | 45|
|
|
|4 | r0 |register_5 | 17|
|
|
|5 | r1 |register_6 | 10|
|
|
|6 | r2 |register_7 | 9|
|
|
|7 | r3 |register_8 | 9|
|
|
|8 | dM |dataMemory | 1|
|
|
|9 | FD |FDModule | 105|
|
|
|10 | CU |ControlUnit | 9|
|
|
|11 | FetchU |FetchUnit | 42|
|
|
|12 | PC |register_3 | 42|
|
|
|13 | RF |RegFile | 54|
|
|
|14 | r0 |register | 9|
|
|
|15 | r1 |register_0 | 27|
|
|
|16 | r2 |register_1 | 9|
|
|
|17 | r3 |register_2 | 9|
|
|
|18 | W |WMUdule | 18|
|
|
|19 | mux5 |mux_2_1 | 18|
|
|
|20 | pipe1 |fDPipReg | 154|
|
|
|21 | pipe2 |eMPipReg | 61|
|
|
+------+-----------+------------+------+
|
|
---------------------------------------------------------------------------------
|
|
Finished Writing Synthesis Report : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
|
|
---------------------------------------------------------------------------------
|
|
Synthesis finished with 0 errors, 0 critical warnings and 6 warnings.
|
|
Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
|
|
Synthesis Optimization Complete : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
|
|
INFO: [Project 1-571] Translating synthesized netlist
|
|
INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
|
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
|
Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00 . Memory (MB): peak = 683.723 ; gain = 0.000
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
|
No Unisim elements were transformed.
|
|
|
|
INFO: [Common 17-83] Releasing license: Synthesis
|
|
80 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|
synth_design completed successfully
|
|
synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 683.723 ; gain = 436.063
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 683.723 ; gain = 0.000
|
|
WARNING: [Constraints 18-5210] No constraints selected for write.
|
|
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
|
INFO: [Common 17-1381] The checkpoint 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.dcp' has been generated.
|
|
INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
|
|
INFO: [Common 17-206] Exiting Vivado at Wed Apr 10 12:50:01 2019...
|