145 lines
4.0 KiB
Verilog
145 lines
4.0 KiB
Verilog
`timescale 1ns / 1ps
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module dataMemory(
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input wire clk, writeEnable,
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input wire [8:0] address, writeData,
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output reg [8:0] readData
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);
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reg [8:0] memory [512:0];
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initial begin
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//Equation Solver Memory
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memory[0] <= 9'b000000001;
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memory[1] <= 9'b000000010;
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// String Compare Memory
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// memory[0] <= 9'b000000100;
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// memory[1] <= 9'b000001000;
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// memory[2] <= 9'b000001100;
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// memory[3] <= 9'b010101010;
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// memory[4] <= 9'b000001111;
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// memory[5] <= 9'b000000100;
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// memory[6] <= 9'b000000000;
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// memory[7] <= 9'b000000111;
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// memory[8] <= 9'b000001111;
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// memory[9] <= 9'b000000110;
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// memory[10] <= 9'b000000010;
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// memory[11] <= 9'b000000000;
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// memory[12] <= 9'b000000000;
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// memory[13] <= 9'b000000000;
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// memory[14] <= 9'b000000000;
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// memory[15] <= 9'b000000000;
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// Bubble Sort Initial Memory
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// memory[0] <= 9'b000011000;
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// memory[1] <= 9'b000000000;
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// memory[2] <= 9'b000100000;
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// memory[3] <= 9'b010001000;
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// memory[4] <= 9'b010010000;
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// memory[5] <= 9'b010011000;
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// memory[6] <= 9'b101001000;
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// memory[7] <= 9'b101001010;
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// memory[8] <= 9'b000100011;
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// memory[9] <= 9'b101001001;
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// memory[10] <= 9'b011001001;
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// memory[11] <= 9'b001001000;
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// memory[12] <= 9'b101001001;
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// memory[13] <= 9'b011101000;
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// memory[14] <= 9'b110001010;
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// memory[15] <= 9'b000100001;
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// memory[16] <= 9'b100110100;
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// memory[17] <= 9'b000001001;
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// memory[18] <= 9'b011001001;
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// memory[19] <= 9'b000110010;
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// memory[20] <= 9'b000000001;
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// memory[21] <= 9'b000111010;
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// memory[22] <= 9'b101011110;
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// memory[23] <= 9'b011111100;
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// Binary Search Memory
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// memory[0] <= 9'b000000000;
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// memory[1] <= 9'b000000111;
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// memory[2] <= 9'b000000001;
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// memory[3] <= 9'b000000010;
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// memory[4] <= 9'b000000011;
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// memory[5] <= 9'b000000100;
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// memory[6] <= 9'b000000101;
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// memory[7] <= 9'b000000110;
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// memory[8] <= 9'b000000111;
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// memory[9] <= 9'b000001000;
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// memory[10] <= 9'b000001001;
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// memory[11] <= 9'b000001010;
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// memory[12] <= 9'b000001011;
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// memory[13] <= 9'b000001100;
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// memory[14] <= 9'b000001101;
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// memory[15] <= 9'b000001110;
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// memory[16] <= 9'b000001111;
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// memory[17] <= 9'b000010000;
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// memory[18] <= 9'b000010001;
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// memory[19] <= 9'b000010010;
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end
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always@(address, clk, memory)begin
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if(clk == 1'b1)begin
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readData <= memory[address];
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if(writeEnable == 1'b1)begin
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memory[address] <= writeData;
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end
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else begin
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memory[address] <= memory[address];
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end
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end
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end
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endmodule
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module dataMemory_tb();
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reg clk, writeEnable;
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reg [8:0] address, writeData;
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wire [8:0] readData;
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initial begin
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clk = 1'b0;
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end
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always begin
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#5 clk = ~clk; // Period to be determined
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end
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dataMemory dM0(
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.clk(clk),
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.writeEnable(writeEnable),
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.writeData(writeData),
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.address(address),
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.readData(readData)
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);
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initial begin
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writeEnable = 1'b0;
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address = 9'b000000000;
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writeData = 9'b010101010;
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#5
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address = 9'b000000100;
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writeData = 9'b010101010;
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#10
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writeEnable = 1'b1;
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address = 9'b000000000;
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writeData = 9'b010101010;
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#10
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address = 9'b000000001;
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writeData = 9'b000001111;
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#10
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address = 9'b000000010;
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writeData = 9'b000000101;
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#10
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address = 9'b000000011;
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writeData = 9'b000000011;
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#10
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address = 9'b00000010;
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writeData = 9'b000001101;
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#5
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$finish;
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end
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endmodule
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