37 lines
725 B
Verilog
37 lines
725 B
Verilog
`timescale 1ns / 1ps
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module ALU(
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input wire [2:0] opcode,
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input wire [8:0] operand0,
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input wire [8:0] operand1,
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output wire [8:0] result
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);
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// Wires for connecting the modules to the mux
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wire [8:0] A,B,C,D,E,F,G,H;
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// A (000) - Add
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// B (001) - Subtract
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// C (010) - OR
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// D (011) - NOR
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// E (100) - AND
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// F (101) - Shift Logical Left
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// G (110) - Shift Logical Right
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// H (111)
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// MUX chooses which result to show based on the OPCODE
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mux_8_1 mux_result(
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.switch(opcode),
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.A(A),
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.B(B),
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.C(C),
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.D(D),
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.E(E),
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.F(F),
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.G(G),
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.H(H),
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.out(result));
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endmodule
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