c047c801aa
Added a decoder and implemented it into the regFile. We probably want to change the testbench so that there arent many changes in one clock cycle. Altered the register file so that it only has the one bit enable decided by the decoder and updated the regFile and fetchUnit to reflect this. Went over the fetch unit with Martin, he said it is okay.
10 lines
227 B
Plaintext
10 lines
227 B
Plaintext
# compile verilog/system verilog design source files
|
|
verilog xil_defaultlib \
|
|
"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \
|
|
|
|
# compile glbl module
|
|
verilog xil_defaultlib "glbl.v"
|
|
|
|
# Do not sort compile order
|
|
nosort
|