3f01492398
There is a testbench but when I try to run it on my computer it brings up some regFile simulation even though SLT is set to top. Not sure if its my pc or the code
10 lines
227 B
Plaintext
10 lines
227 B
Plaintext
# compile verilog/system verilog design source files
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verilog xil_defaultlib \
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"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \
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# compile glbl module
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verilog xil_defaultlib "glbl.v"
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# Do not sort compile order
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nosort
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