jose.rodriguezlabra eeb9c7c318 Tested zero

2019-03-16 14:55:11 -04:00

..

ALU.v

Added zeroing instr

2019-03-16 14:34:36 -04:00

BasicModules.v

Added zeroing instr

2019-03-16 14:34:36 -04:00

ControlUnit.v

Added zeroing instr

2019-03-16 14:34:36 -04:00

CPU9bits.v

Tested zero

2019-03-16 14:55:11 -04:00

dataMemory.v

Instruction & Data Memory

2019-03-16 14:16:02 -04:00

FetchUnit.v

Better Sim

2019-03-14 14:37:58 -04:00

instructionMemory.v

Instruction & Data Memory

2019-03-16 14:16:02 -04:00

RegFile.v

Fixed bugs, finished BEQ, Added Halt

2019-03-13 11:14:52 -04:00