WilliamMiceli f4c923f60c Fixed ALU to use the inputs we're actually going to be giving it

2019-02-15 16:19:42 -05:00

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ALU.v

Fixed ALU to use the inputs we're actually going to be giving it

2019-02-15 16:19:42 -05:00

BasicModules.v

Added 1-bit and 9-bit OR and NOR modules

2019-02-15 16:16:13 -05:00

fetchFile.v

fetch unit

2019-02-15 11:20:14 -05:00

FetchUnit.v

Modularized project; mux, clock, and reg done; Progress on RegFile

2019-02-15 12:24:26 -05:00

lab2testing.v

Modularized project; mux, clock, and reg done; Progress on RegFile

2019-02-15 12:24:26 -05:00

RegFile.v

Removed comment blocks

2019-02-15 14:34:59 -05:00