WilliamMiceli f4c923f60c Fixed ALU to use the inputs we're actually going to be giving it

2019-02-15 16:19:42 -05:00

lab2CA.cache/wt

Added 1-bit adder

2019-02-15 14:55:11 -05:00

lab2CA.ip_user_files

fetch unit

2019-02-15 11:20:14 -05:00

lab2CA.srcs/sources_1/new

Fixed ALU to use the inputs we're actually going to be giving it

2019-02-15 16:19:42 -05:00

.gitignore

Initial commit, gitignore

2019-02-08 18:10:13 -05:00

lab2CA.xpr

Added 1-bit and 9-bit OR and NOR modules

2019-02-15 16:16:13 -05:00

vivado.jou

Forgot to stage this file

2019-02-15 11:53:54 -05:00

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