48 lines
832 B
Verilog
48 lines
832 B
Verilog
`timescale 1ns / 1ps
|
|
|
|
module CPU9bits(input wire [8:0] instr,
|
|
input wire reset, clk,
|
|
output reg done
|
|
);
|
|
|
|
wire [8:0] op1, op2;
|
|
|
|
RegFile RF(
|
|
.clk(clk),
|
|
.reset(reset),
|
|
.enable(),
|
|
.write_index(),
|
|
.op0_idx(),
|
|
.op1_idx(),
|
|
.write_data(),
|
|
.op0(op0),
|
|
.op1(op1)
|
|
);
|
|
|
|
FetchUnit FU(
|
|
.clk(clk),
|
|
.reset(reset),
|
|
.op_idx(),
|
|
.AddrIn(),
|
|
.AddrOut()
|
|
);
|
|
|
|
ALU alu(
|
|
.opcode(),
|
|
.operand0(op0),
|
|
.operand1(op1),
|
|
.result()
|
|
);
|
|
|
|
//Make control unit here
|
|
|
|
always @(instr) begin
|
|
case (instr)
|
|
9'b000000000: //something
|
|
endcase
|
|
end
|
|
|
|
//------------------------------
|
|
|
|
endmodule
|