William/Senior-Design-Project_WMU-Sunseeker_Code
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William Miceli
2021-06-07 17:14:43 -04:00
parent b9fff39940
commit 8cd4c6962c
1 changed files with 6 additions and 3 deletions
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9
Telem_Debug/Debug_UART-USB/usci.c
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@@ -22,7 +22,6 @@ void usci_A0_init(void){
/******************************** USCI A1 ********************************/
/*************************************************************************/
void usci_A1_init(void){
}
@@ -32,7 +31,7 @@ void usci_A1_init(void){
/*************************************************************************/
void usci_A2_init(void){
UCA2CTL1 |= UCSWRST; // Software Reset Enable - Set high, disabling the USCI module; Register options can only be set when the UCSWRST bit = 1
UCA2CTL1 |= UCSWRST; // Software Reset Enable - Set high, disabling the USCI module; USCI configuration changes can only be made when the UCSWRST bit = 1
UCA2CTL1 &= ~0b11000000; // Reset both UCSSELx bits so the USCI Clock Source Select bits are more predictable
UCA2CTL1 |= UCSSEL__SMCLK; // USCI Clock Source Select - SMCLK
UCA2CTL1 &= ~UCRXEIE; // Receive Erroneous-Character Interrupt Enable - Disabled
@@ -47,7 +46,11 @@ void usci_A2_init(void){
UCA2CTL0 &= ~UCMODE1; // USCI Mode [2 Bits Required] - UART mode selected
UCA2CTL0 &= ~UCMODE0; // USCI Mode [2 Bits Required] - UART mode selected
UCA2CTL0 &= ~UCSYNC; // Synchronous Mode Enable - Asynchronous mode selected
UCA2BRW = 10; // Clock Prescalar
UCA2MCTL &= ~0b11111111; // Reset entire register
UCA2MCTL |= 0x0 << 4; // First Modulation Stage Select
UCA2MCTL |= 0x0 << 1; // Second Modulation Stage Select
UCA2MCTL |= 0x0; // Oversampling Mode Enable - Disabled
}
void usci_A2_enable(void){