Fixed bugs, finished BEQ, Added Halt
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@@ -41,7 +41,7 @@ module RegFile(input wire clk, reset, enable,
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register r3(
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.clk(clk),
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.reset(reset),
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.En(decOut[4]),
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.En(decOut[3]),
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.Din(write_data),
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.Dout(r3_out));
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