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Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2

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# Conflicts:
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
#	lab2CA.srcs/sources_1/new/dataMemory.v
#	lab2CA.srcs/sources_1/new/instructionMemory.v
#	lab2CA.xpr
This commit is contained in:
Johannes
2019-03-24 17:08:42 -04:00
parent 03df69372a 8e72409386
commit 033e606d5d
5 changed files with 230 additions and 7 deletions
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69
lab2CA.srcs/sources_1/new/dataMemory.v
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@@ -26,6 +26,73 @@ module dataMemory(
memory[13] <= 9'b000000000;
memory[14] <= 9'b000000000;
memory[15] <= 9'b000000000;
// // String Compare Memory
// memory[0] <= 9'b000000100;
// memory[1] <= 9'b000001000;
// memory[2] <= 9'b000001100;
// memory[3] <= 9'b010101010;
// memory[4] <= 9'b000001111;
// memory[5] <= 9'b000000100;
// memory[6] <= 9'b000000011;
// memory[7] <= 9'b000000000;
// memory[8] <= 9'b000001111;
// memory[9] <= 9'b000000100;
// memory[10] <= 9'b000000010;
// memory[11] <= 9'b000000000;
// memory[12] <= 9'b000000000;
// memory[13] <= 9'b000000000;
// memory[14] <= 9'b000000000;
// memory[15] <= 9'b000000000;
// Bubble Sort Initial Memory
memory[0] <= 9'b000011000;
memory[1] <= 9'b000000000;
memory[2] <= 9'b000100000;
memory[3] <= 9'b010001000;
memory[4] <= 9'b010010000;
memory[5] <= 9'b010011000;
memory[6] <= 9'b101001000;
memory[7] <= 9'b101001010;
memory[8] <= 9'b000100011;
memory[9] <= 9'b101001001;
memory[10] <= 9'b011001001;
memory[11] <= 9'b001001000;
memory[12] <= 9'b101001001;
memory[13] <= 9'b011101000;
memory[14] <= 9'b110001010;
memory[15] <= 9'b000100001;
memory[16] <= 9'b100110100;
memory[17] <= 9'b000001001;
memory[18] <= 9'b011001001;
memory[19] <= 9'b000110010;
memory[20] <= 9'b000000001;
memory[21] <= 9'b000111010;
memory[22] <= 9'b101011110;
memory[23] <= 9'b011111100;
// Binary Search Memory
// memory[0] <= 9'b000000000;
// memory[1] <= 9'b000000111;
// memory[2] <= 9'b000000001;
// memory[3] <= 9'b000000010;
// memory[4] <= 9'b000000011;
// memory[5] <= 9'b000000100;
// memory[6] <= 9'b000000101;
// memory[7] <= 9'b000000110;
// memory[8] <= 9'b000000111;
// memory[9] <= 9'b000001000;
// memory[10] <= 9'b000001001;
// memory[11] <= 9'b000001010;
// memory[12] <= 9'b000001011;
// memory[13] <= 9'b000001100;
// memory[14] <= 9'b000001101;
// memory[15] <= 9'b000001110;
// memory[16] <= 9'b000001111;
// memory[17] <= 9'b000010000;
// memory[18] <= 9'b000010001;
// memory[19] <= 9'b000010010;
end
always@(address, clk, memory)begin
@@ -87,4 +154,4 @@ module dataMemory_tb();
#5
$finish;
end
endmodule
endmodule