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This commit is contained in:
jose.rodriguezlabra
2019-02-15 12:38:07 -05:00
parent 7aa2cfff2a
commit 0b358a6c41
57 changed files with 3092 additions and 86 deletions
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11
lab2CA.sim/sim_1/impl/timing/xsim/RegFile.tcl Normal file
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set curr_wave [current_wave_config]
if { [string length $curr_wave] == 0 } {
if { [llength [get_objects]] > 0} {
add_wave /
set_property needs_save false [current_wave_config]
} else {
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
}
}
run 1000ns

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lab2CA.sim/sim_1/impl/timing/xsim/RegFile_time_impl.v Normal file
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// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
// Date : Fri Feb 15 12:36:16 2019
// Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
// Command : write_verilog -mode timesim -nolib -sdf_anno true -force -file {C:/Users/JoseIgnacio/CA
// Lab/lab2CA.sim/sim_1/impl/timing/xsim/RegFile_time_impl.v}
// Design : RegFile
// Purpose : This verilog netlist is a timing simulation representation of the design and should not be modified or
// synthesized. Please ensure that this netlist is used with the corresponding SDF file.
// Device : xc7k160tifbg484-2L
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
`define XIL_TIMING
(* ECO_CHECKSUM = "2b285f13" *)
(* NotValidForBitStream *)
module RegFile
(clk,
reset,
write_index,
op0_idx,
op1_idx,
write_data,
op0,
op1);
input clk;
input reset;
input [1:0]write_index;
input [1:0]op0_idx;
input [1:0]op1_idx;
input [8:0]write_data;
output [8:0]op0;
output [8:0]op1;
wire [8:0]op0;
wire [8:0]op1;
initial begin
$sdf_annotate("RegFile_time_impl.sdf",,,,"tool_control");
end
OBUFT \op0_OBUF[0]_inst
(.I(1'b0),
.O(op0[0]),
.T(1'b1));
OBUFT \op0_OBUF[1]_inst
(.I(1'b0),
.O(op0[1]),
.T(1'b1));
OBUFT \op0_OBUF[2]_inst
(.I(1'b0),
.O(op0[2]),
.T(1'b1));
OBUFT \op0_OBUF[3]_inst
(.I(1'b0),
.O(op0[3]),
.T(1'b1));
OBUFT \op0_OBUF[4]_inst
(.I(1'b0),
.O(op0[4]),
.T(1'b1));
OBUFT \op0_OBUF[5]_inst
(.I(1'b0),
.O(op0[5]),
.T(1'b1));
OBUFT \op0_OBUF[6]_inst
(.I(1'b0),
.O(op0[6]),
.T(1'b1));
OBUFT \op0_OBUF[7]_inst
(.I(1'b0),
.O(op0[7]),
.T(1'b1));
OBUFT \op0_OBUF[8]_inst
(.I(1'b0),
.O(op0[8]),
.T(1'b1));
OBUFT \op1_OBUF[0]_inst
(.I(1'b0),
.O(op1[0]),
.T(1'b1));
OBUFT \op1_OBUF[1]_inst
(.I(1'b0),
.O(op1[1]),
.T(1'b1));
OBUFT \op1_OBUF[2]_inst
(.I(1'b0),
.O(op1[2]),
.T(1'b1));
OBUFT \op1_OBUF[3]_inst
(.I(1'b0),
.O(op1[3]),
.T(1'b1));
OBUFT \op1_OBUF[4]_inst
(.I(1'b0),
.O(op1[4]),
.T(1'b1));
OBUFT \op1_OBUF[5]_inst
(.I(1'b0),
.O(op1[5]),
.T(1'b1));
OBUFT \op1_OBUF[6]_inst
(.I(1'b0),
.O(op1[6]),
.T(1'b1));
OBUFT \op1_OBUF[7]_inst
(.I(1'b0),
.O(op1[7]),
.T(1'b1));
OBUFT \op1_OBUF[8]_inst
(.I(1'b0),
.O(op1[8]),
.T(1'b1));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif

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lab2CA.sim/sim_1/impl/timing/xsim/RegFile_vlog.prj Normal file
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# compile verilog/system verilog design source files
verilog xil_defaultlib \
"RegFile_time_impl.v" \
# Do not sort compile order
nosort

12
lab2CA.sim/sim_1/impl/timing/xsim/webtalk.jou Normal file
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#-----------------------------------------------------------
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Fri Feb 15 12:37:49 2019
# Process ID: 17624
# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/impl/timing/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/RegFile_time_impl/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/impl/timing/xsim/webtalk.log
# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/impl/timing/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/Users/JoseIgnacio/CA -notrace

12
lab2CA.sim/sim_1/impl/timing/xsim/webtalk_2004.backup.jou Normal file
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#-----------------------------------------------------------
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Fri Feb 15 12:36:24 2019
# Process ID: 2004
# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/impl/timing/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/RegFile_time_impl/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/impl/timing/xsim/webtalk.log
# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/impl/timing/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/Users/JoseIgnacio/CA -notrace

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lab2CA.sim/sim_1/impl/timing/xsim/xelab.pb Normal file
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lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/RegFile_time_impl/Compile_Options.txt Normal file
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-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" --maxdelay -L "xil_defaultlib" -L "simprims_ver" -L "secureip" --snapshot "RegFile_time_impl" -transport_int_delays -pulse_r "0" -pulse_int_r "0" -pulse_e "0" -pulse_int_e "0" "xil_defaultlib.RegFile" "xil_defaultlib.glbl" -log "elaborate.log"

1
lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/RegFile_time_impl/TempBreakPointFile.txt Normal file
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Breakpoint File Version 1.0

148
lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/RegFile_time_impl/obj/xsim_1.c Normal file
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
typedef void (*funcp)(char *, char *);
extern int main(int, char**);
extern void execute_2(char*, char *);
extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*);
extern void execute_4(char*, char *);
extern void execute_43(char*, char *);
extern void execute_44(char*, char *);
extern void execute_45(char*, char *);
extern void execute_46(char*, char *);
extern void execute_40(char*, char *);
extern void execute_41(char*, char *);
extern void execute_42(char*, char *);
extern void execute_151(char*, char *);
extern void execute_152(char*, char *);
extern void execute_153(char*, char *);
extern void execute_154(char*, char *);
extern void execute_155(char*, char *);
extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
extern void transaction_6(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_7(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_8(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_9(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_10(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_11(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_12(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_13(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_14(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_15(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_16(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_17(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_18(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_19(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_20(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_21(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_22(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_23(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_24(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_25(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_26(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_27(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_28(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_29(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_30(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_31(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_32(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_33(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_34(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_35(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_36(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_37(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_38(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_39(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_40(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_41(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_42(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_43(char*, char*, unsigned, unsigned, unsigned);
funcp funcTab[54] = {(funcp)execute_2, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_4, (funcp)execute_43, (funcp)execute_44, (funcp)execute_45, (funcp)execute_46, (funcp)execute_40, (funcp)execute_41, (funcp)execute_42, (funcp)execute_151, (funcp)execute_152, (funcp)execute_153, (funcp)execute_154, (funcp)execute_155, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_6, (funcp)transaction_7, (funcp)transaction_8, (funcp)transaction_9, (funcp)transaction_10, (funcp)transaction_11, (funcp)transaction_12, (funcp)transaction_13, (funcp)transaction_14, (funcp)transaction_15, (funcp)transaction_16, (funcp)transaction_17, (funcp)transaction_18, (funcp)transaction_19, (funcp)transaction_20, (funcp)transaction_21, (funcp)transaction_22, (funcp)transaction_23, (funcp)transaction_24, (funcp)transaction_25, (funcp)transaction_26, (funcp)transaction_27, (funcp)transaction_28, (funcp)transaction_29, (funcp)transaction_30, (funcp)transaction_31, (funcp)transaction_32, (funcp)transaction_33, (funcp)transaction_34, (funcp)transaction_35, (funcp)transaction_36, (funcp)transaction_37, (funcp)transaction_38, (funcp)transaction_39, (funcp)transaction_40, (funcp)transaction_41, (funcp)transaction_42, (funcp)transaction_43};
const int NumRelocateId= 54;
void relocate(char *dp)
{
iki_relocate(dp, "xsim.dir/RegFile_time_impl/xsim.reloc", (void **)funcTab, 54);
/*Populate the transaction function pointer field in the whole net structure */
}
void sensitize(char *dp)
{
iki_sensitize(dp, "xsim.dir/RegFile_time_impl/xsim.reloc");
}
void simulate(char *dp)
{
iki_schedule_processes_at_time_zero(dp, "xsim.dir/RegFile_time_impl/xsim.reloc");
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
iki_execute_processes();
// Schedule resolution functions for the multiply driven Verilog nets that have strength
// Schedule transaction functions for the singly driven Verilog nets that have strength
}
#include "iki_bridge.h"
void relocate(char *);
void sensitize(char *);
void simulate(char *);
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
extern void implicit_HDL_SCinstatiate();
extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
int main(int argc, char **argv)
{
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
iki_set_sv_type_file_path_name("xsim.dir/RegFile_time_impl/xsim.svtype");
iki_set_crvs_dump_file_path_name("xsim.dir/RegFile_time_impl/xsim.crvsdump");
void* design_handle = iki_create_design("xsim.dir/RegFile_time_impl/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv);
iki_set_rc_trial_count(100);
(void) design_handle;
return iki_simulate_design();
}

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lab2CA.sim/sim_1/impl/timing/xsim/xvlog.pb Normal file
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